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Realtek
RTD2523/2513
RTD2523/2513 Flat Panel Display Controller
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Confidential Revision 0.18 March 19, 2004
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Revision History Rev.
0.18 l l
RTD2523/2513 Description Date
March 2004
Pin-Description modification of TCON function in TTL output interface Explanation for register DV_Total
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1. Features
General
l l l l l l l l Embedded dual DDC support DDC1, DDC2B, DDC/CI Zoom scaling up and down Embedded Pattern Generator No external memory required. Require only one crystal to generate all timing Embedded reset control output Embedded crystal output to MICROP 3 channels 8 bits PWM output, and selectable PWM clock frequency.
RTD2523/2513
Color Processor
l l l l Digital brightness and contrast adjustments sRGB compliance Gamma correction Dithering logic for 18-bit panel color depth enhancement
Output Interface
l l l l l l l l l Built-in display timing generator and fully programmable (RTD2523) 1 and 2-pixel/clock panel support and up to 140MHz (RTD2513) 1 and 2-pixel/clock panel support and up to 95MHz Scaler internal LSB/MSB swap, odd/even swap and red/blue group swap. Programmable TCON function support RSDS (Reduced Swing Differential Signaling) data bus type 1~3. Dual/Single LVDS interface output Reduced EMI and power saving feature Integrated Spread-Spectrum DCLK PLL.
Analog RGB Input Interface
l l l l l l Integrated 8-bit triple-channel 140MHz ADC/PLL Support up to 140MHz (SXGA@ 75Hz) Embedded programmable Schmitt trigger of HSYNC Support Sync On Green (SOG) and de-composite sync modes On-chip high-performance PLLs 32 phase APLL
Digital Input Interface
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Host Interface
l l Support MCU serial bus interface Support MCU parallel bus interface
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Support 8-bit video (ITU 656) format input Built-in YUV to RGB color space converter & de-interlace
DVI Compliant Digital Input Interface
l l l Single link on-chip TMDS receiver Operation up to 165Mhz Direct connect to DVI compliant TMDS transmitter
Embedded OSD
l l l l l l l l l Embedded 11.25K SRAM dynamically stores OSD command and fonts Support multi-color RAM font, 1, 2 and 4-bit per pixel 16 color palette with 24bit true color selection Maximum 8 window with alpha-blending/ gradient/dynamic fade-in/fade-out, bordering/ shadow/3D window type Every window can place anywhere on the screen Rotary 90,180,270 degree Independent row shadowing/bordering Programmable blinking effects for each character OSD-made internal pattern generator for factory mode Support 12x18~4x18 proportional font
Auto Detection /Auto Calibration
l l l Input format detection Compatibility with standard VESA mode and support user-defined mode Smart engine for Phase and Image position calibration
Scaling
l l l l Fully programmable zoom ratios Independent horizontal/vertical scaling Advanced zoom algorithm provides high image quality Sharpness/Smooth filter enhancement
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Power & Technology
2.5V/3.3V power supplier 0.25um CMOS process; 128-pin QFP package.
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2. RTD2523/2513 Pin-Out Diagram
GNDK VCCK DDCSCL2 / TCON[5] DDCSDA2 / TCON[7] TCON[0] / VCLK / DCLK TCON[1] / V[7] /DENA TCON[5] / V[6] / DVS VCCIO GNDIO TCON[6] / V[5] DHS TCON[7] / V[4] TCON[8] / V[3] TCON[9] / V[2] TCON[10] / V[1] TCON[11] / V[0] TCON[12]/COUT/PWM2 REFCLK / PWM0 SCSB PVCC PGND AR1N AR1P AR2N AR2P AR3N AR3P
RTD2523/2513
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:LVDS+RSDS+TTLO :RSDS+TTLO :TTLO (TCON)
ADC_GND ADC_GND ADC_VDD AHS AVS GNDK VCCK DDCSCL / TCON[0] DDCSDA/TCON[1]/PWM1 GNDIO VCCIO SCLK TCON[2] /SDIO[3] / PWM2 TCON[3] / SDIO[2] TCON[4] / SDIO[1] SDIO[0] TCON[13] / COUT / PWM2 RESET PGND PVCC BB3P BB3N BB2P BB2N BB1P BB1N
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
XO XI DPLL_GND DPLL_VDD APLL_VDD PLL_TST1 PLL_TST2 APLL_GND TMDS_TST/PWM1 TMDS_GND TMDS_VDD REXT TMDS_VDD RX2P RX2N TMDS_GND RX1P RX1N TMDS_VDD RX0P RX0N TMDS_GND RXCP RXCN TMDS_GND TMDS_VDD ADC_GND ADC_REFIO ADC_VDD B+ BADC_GND SOG G+ GADC_VDD R+ R-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
RTD2523
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AG1N AG1P AG2N AG2P VCCK GNDK PGND PVCC AG3N AG3P ACLKN ACLKP AB1N AB1P AB2N AB2P AB3N AB3P PGND PVCC BR1N BR1P BR2N BR2P BR3N BR3P BG1N BG1P BG2N BG2P PGND PVCC GNDK VCCK BG3N BG3P BCLKN BCLKP
:TTLIO (TCON / VIDEO) :TTLIO (DDC / TCON) Figure 1 Pin-Out Diagram ( 6-bit Dual RSDS ) 4
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(I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground) n ADC: 15 pins
Name ADC_GND ADC_REFIO ADC_VDD BLUE+ BLUEADC_GND SOG/ADC_TEST GREEN+ GREENADCB_VDD RED+ REDADC_GND ADC_GND ADC_VDD AHS AVS I/O AG AP AP AI AI AG AIO AI AI AP AI AI AG AG AP AI AI Pin No 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Description ADC ground ADC band-gap voltage de-coupling Analog power Analog input from BLUE channel Analog input ground from BLUE channel ADC ground SOG in/ADC test pin Analog input from GREEN channel Analog input ground from GREEN channel Analog power Analog input from RED channel Analog input ground from RED channel Analog ground Analog ground Analog power Analog HS input Analog VS input
RTD2523/2513
Note 1.20V (3.3V)
(3.3V)
(3.3V) (10), (4), (5) (2), (4), (5)
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PLL: 8 pins
Name XO XI DPLL_GND DPLL_VDD APLL_VDD PLL_TEST1 PLL_TEST2 APLL_GND I/O AI AO AG AP AP AIO AIO AG Pin No 1 2 3 4 5 6 7 8 Description Reference clock output Reference clock input Ground for digital PLL Power for digital PLL Power for multi-phase PLL Test Pin 1 / IRQ# Test Pin 2/Power-on-latch for crystal out Frequency Ground for multi-phase PLL Note
(3.3V) (3.3V) 3.3V tolerance
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Control Interface: 7 pins
Name SDIO [0] SDIO [1] / TCON [4] / BBLU [0] SDIO [2] / TCON [3] / BBLU [1] SDIO [3] / PWM2 / TCON [2] SCLK SCSB RESET I/O IO IO IO IO I I O Pin No 54 53 52 51 50 111 56 Description Serial control I/F data in / Parallel port data [0] Parallel port data [1] / TCON [4] / TTL BBLU [0] Parallel port data [2] / TCON [3] / TTL BBLU [1] Parallel port data [1] / TCON [4] / PWM2 Serial control I/F clock Serial control I/F chip select RESET output for Micron Note (2), (3), / 2mA (1), (2), (3), / 2mA (1), (2), (3), / 2mA (1), (2), (3), / 2mA (2), (3), (5) (2), (3), (5) (2), (5), (6) / 2mA
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n Pin NO . 51 6-bits Dual RSDS S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BB3P BB3N BB2P BB2N BB1P BB1N BCLKP BCLKN BG3P BG3N BG2P BG2N BG1P BG1N BR3P BR3N BR2P BR2N BR1P BR1N AB3P AB3N 6 bits Single RSDS S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13]
BB3P BB3N BB2P BB2N BB1P BB1N BCLKP BCLKN BG3P BG3N
RTD2523/2513
Display & TCON/VIDEO-8 Port: 54 pins :LVDS+RSDS+TTLO :RSDS+TTLO :RSDS+TTLIO:TTLO :TTLIO
8/6 bits Dual/Single LVDS S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] NC NC NC NC NC NC NC NC NC NC TODP TODN TOCLKP TOCLKN TOCP TOCN TOBP TOBP TOAP TOAP TEDP TEDN 8 bits Dual/Single TTL S[3] / TCON[2] / PWM2 S[2] /BBLU[1] / TCON[3] S[1]/ BBLU[0] / TCON[4] PWM2 / COUT / TCON[13] BBLU [7] BBLU [6] BBLU [5] BBLU [4] BBLU [3]/T0 BBLU [2] / T1 BGRN [1] / T2 BGRN [0] / T3 BGRN[7] BGRN[6] BGRN [5] / T4 BGRN [4] / T5 BGRN [3] / T6 BGRN [2] / T7 BRED [7] / T8 BRED [6] / T9 BRED [5] / T10 BRED [4] / T11 BRED [3] / T12 BRED [2] / T13 ABLU [7] / T14 ABLU [6] / T15 6 bits Dual TTL S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BBLU [7] BBLU [6] BBLU [5] BBLU [4] BBLU [3] BBLU [2] TCON [6] TCON [5] BGRN [7] BGRN [6] BGRN [5] BGRN [4] BGRN [3] BGRN [2] BRED [7] BRED [6] BRED [5] BRED [4] BRED [3] BRED [2] ABLU [7] ABLU [6] 6 bits Single TTL S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BBLU [7] BBLU [6] BBLU [5] BBLU [4] BBLU [3] BBLU [2] TCON [6] TCON [5] BGRN [7] BGRN [6] BGRN [5] BGRN [4] BGRN [3] BGRN [2] BRED [7] BRED [6] BRED [5] BRED [4] BRED [3] BRED [2] ABLU [7] ABLU [6] Note
(1), (2), (3)/ 2mA (1), (2), (3)/ 2mA (1), (2), (3)/ 2mA (1), (2), (3)/ 2mA
52
53
55
59 60 61 62 63 64 65
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66 67 68 73 74 75 76 77 78 79 80 81 82 85 86
BG2P BG2N BG1P BG1N BR3P BR3N BR2P BR2N BR1P BR1N NC NC
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87 88 89 90 91 92 93 94 99 100 101 102 103 104
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RTD2523/2513
NC NC NC NC NC NC NC NC TCON [11] TCON [10] TCON [9] TCON [8] TCON [7] TCON [6] TCON [5] TCON [1] TCON [0] NC PWM2 / COUT / TCON[12] V [0] V [1] V [2] V [3] V [4] V [5] V [6] V [7] VCLK TECLKP TECLKN TECP TECN TEBP TEBN TEAP TEAN NC NC NC NC NC NC NC NC NC NC PWM2 / COUT / TCON[12] V [0] V [1] V [2] V [3] V [4] V [5] V [6] V [7] VCLK ABLU [5] / T16 ABLU [4] / T17 ABLU [3] / T18 ABLU [2] / T19 ABLU [1] / T20 ABLU [0] / T21 AGRN [7] / T22 AGRN [6] / T23 AGRN [5] / T24 AGRN [4] / T25 AGRN [3] / T26 AGRN [2] / T27 ARED [7] / T28 ARED [6] / T29 ARED [5] / TH ARED [4] / TV ARED [3] / TE ARED [2] / TK ARED [1] ABLU [5] ABLU [4] ABLU [3] ABLU [2] TCON [1] TCON [0] AGRN [7] AGRN [6] AGRN [5] AGRN [4] AGRN [3] AGRN [2] ARED [7] ARED [6] ARED [5] ARED [4] ARED [3] ARED [2] COUT ABLU [5] ABLU [4] ABLU [3] ABLU [2] TCON [1] TCON [0] AGRN [7] AGRN [6] AGRN [5] AGRN [4] AGRN [3] AGRN [2] ARED [7] ARED [6] ARED [5] ARED [4] ARED [3] ARED [2] PWM2 / COUT / TCON[12] TCON [11] TCON [10] TCON [9] TCON [8] TCON [7] DHS DVS DENA DCLK DHS DVS DENA DCLK (9)
AB2P AB2N AB1P AB1N ACLKP ACLKN AG3P AG3N AG2P AG2N AG1P AG1N AR3P AR3N AR2P AR2N AR1P AR1N PWM2 / COUT / TCON[12] TCON [11] /V[0] TCON [10] /V[1] TCON [9] / V[2] TCON [8] / V[3] TCON [7] / V[4] TCON [6] / V[5] TCON [5] / V[6] TCON [1] / V[7] TCON [0] / VCLK
105 106 107 108 113
114 115 116 117 118 119 122 123 124
ARED [0] BRED [1] BRED [0] AGRN [1] AGRN [0] DHS DVS DENA DCLK
(1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8)
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RTD2523/2513
* Single RSDS, even/odd swap, data(59~82) output to pin85~108, TCON(99~108) output to pin59~68. * In 6-bit dual TTL output mode, Video8 cannot output TCON7~TCON11; while video8 can output TCON in 6-bit single TTL mode.
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TMDS: 18 pins
Name TMDS_TST/ PWM1 TMDS_GND TMDS_VDD EXT_RES TMDS_VDD RX2P RX2N TMDS_GND RX1P RX1N TMDS_VDD RX0P RX0N TMDS_GND RXCP RXCN TMDS_GND TMDS_VDD I/O AIO G P A P I I G I I P I I G I I G P Pin No 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description TMDS_TEST Pin / PWM1 / Power-on-latch for serial / parallel port Note
(3.3V) Impedance Match Reference. (3.3V) Differential Data Input Differential Data Input Differential Data Input Differential Data Input (3.3V) Differential Data Input Differential Data Input Differential Data Input Differential Data Input (3.3V)
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PWM Interface: (PWM1, PWM2 can be selected from 1 of 3 possible pins.)
Name PWM2 / TCON [2] / S [3] PWM2 / TCON [13] / COUT PWM2 / TCON [12] / COUT PWM1 / TMDS_TST PWM1 / DDCSDA / TCON [1] / BBLU [0] PWM1 / DDCSDA2 / TCON [7] PWM0 / REFCLK I/O O O O Pin No 51 55 113 Description PWM2 / TCON [2] / SDIO [3] PWM2 / TCON [13] / Crystal out PWM2 / TCON [12] / Crystal out Note (1), (2), (3), (5), (8), (2), (8), (9) (2), (8), (9) 6bit dual TTL cannot support (2), (7), (8) (1), (2), (3), (5), (8), (1), (2), (3), (5), (8), (2), (9)
AIO IO IO IO
9 47 125 112
PWM1/ TMDS_TEST Pin / Power-on-latch for serial / parallel port PWM1 / DDC serial control I/F data input / output / TCON [4] PWM1 / DDC serial control I/F data input / output / TCON [7] PWM0 / (In / out) test pin for DCLK / Video8 even-odd signal
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DDC Channel: 4 pins
Name DDCSCL / TCON [0] / BBLU [1] DDCSDA / TCON [1] / PWM1 / BBLU [0] DDCSCL2 / TCON [5] DDCSDA2 / TCON [7] /PWM1 I/O I IO I IO Pin No 46 47 126 125 Description DDC serial control I/F clock / TCON [0] / TTL BBLU [1] DDC serial control I/F data input / output / TCON [1] / PWM1 / TTL BBLU [0] DDC serial control I/F clock / TCON [5] DDC serial control I/F data input / output / TCON [7] / PWM1 Note (2), (3), (5) (1), (2), (3), (5), (6), (8)/ 8mA /no slew (2), (3), (5) (1), (2), (3), (5), (6), (8)/ 8mA /no slew
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n Power & Ground: 22 pins
Name I/O Pin No 3.3V Power P 49,121 VCCIO: 2 G 3.3V Ground 48,120 GNDIO: 2 P 3.3V Power 58,71,83,95,110 PVCC: 5 G 3.3V Ground 57,72,84,96,109 PGND: 5 2.5V Power P 45,69,98,127 VCCK: 4 G 2.5V Ground 44,70,97,128 GNDK: 4 Note: (1) TTL compatible CMOS Input (Vt=1.7V); VCC=3.3V; (2) 5V tolerance pad; (3) Internal 75K Ohms pull high resistor. (4) Internal 75K Ohms pull low resistor. (5) Schmitt trigger CMOS Input (Vt=1.4-~2.2V); (6) Open-Drain, Output Drive low & Pull-high. (7) Bi-directional input/output (8) Programmable driving current (2~10mA) (9) TTL output 5V & 3.3V (10) 4V tolerance pad
RTD2523/2513
Description
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3. General Description
DDC TCON 5C 48D RTD2523 Flat Panel Display
RTD2523/2513
VS HS R/G/B Rx0~2 RxC Video Decoder 1C 8D 24.576MHz Parallel Port
LCD Panel Row/Column Driver
5C 48D
TTL Signal LCD Panel
48D 5C 20
RSDS Signal LCD Panel
Reset 24.576MHz IIC
MCU
LVDS Signal LCD Panel
Figure 2 Application System Block Diagram
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Analog RGB Digital DVI ITU-656
Triple-ADC FIFO TMDS/ HDCP
Color Conversion
Timing Control
Panel Driver
HS & VS
Sync Processor
Control Register
Scaling Up
Build-In OSD
PLL 24.576MHz
Color Processing
OSD MUX
Panel
MCU Figure 3 Chip Functional Block Diagram
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4. Functional Description
4.1 Input
RTD2523/2513
Digital Input (ITU 656) RTD is designed to connect the interface of digital signal from video decoder. Input data is latched within a capture window defined in registers. The timing scheme designed for input devices are showed in the following diagram. There are not H syncV sync signals provided by the video decoder with ITU BT.656, these synchronal signals have to be generated by decoding the EAV & SAV timing reference signals.
VGBCLK VGB_R(Byte)
xxx U0 Y0 V0 Y1 U2
Figure 4 Input YUV 4:2:2(8-bits) Timing Only 254 of possible 256 8-bit words may be used to express a signal value, 0 and 255 are reserved for data identification purposes. Video 8 data stream is as below:
Blanking Timing reference 720 pixels YUV 422 DATA period code ... 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 ... Cbn: U(B-Y) colour difference component Yn : luminance component Crn: V(R-Y) colour difference component Timing reference Blanking code period Cr718 Y719 FF 00 00 EAV 80 10 ...
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SAV/EAV format Bit 7 Bit 6(F) 1 Field bit 1st field F=0 2nd field F=1
Bit 5(V) Bit 4(H) Bit 3(P3) Bit 2(P2) Bit 1(P1) Bit 0(P0) Vertical blanking bit V=1 H=0 in SAV Protection bits Active video V=0 H=1 in EAV
Hardware can recognize the occurrence of EAV & SAV by detecting the 0xff , 0x00 , 0x00 data sequence, and then generate the HsyncVsyncField signals internally by decoding the fourth word of the timing reference signal(EAVSAV). F & V change state synchronously with the EAV(End of active video) reference code at the beginning of the digital line. Bits P0, P1, P2, P3, have states dependent on the states of the bits F, V and H as shown below. At the receiver this permits one-bit errors to be corrected and two-bits errors to be detected.
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RTD2523/2513
Error correction A = P1 xor F xor V B = P2 xor F xor H C = P3 xor V xor H D = F xor V xor H xor P3 xor P2 xor P1 xor P0 F' = F xor (DA BC# ) V' = V xor (DAB#C) H' = H xor (DA#BC) SAV/EAV one-bit error occurs when D(A + B + C) SAV/EAV two-bit error occurs when D#(A + B + C)
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Analog Input RTD integrates three ADC' (analog-to-digital converters), one for each color (red, green, and blue). s The sync-processor can deal with Separate-Sync, Composite-Sync, and Sync-On-Green. And the PLL can generate very low jitter clock from HS to sample the analog signal to digital data. Input data is latched within a capture window defined in registers refer to VS and HS leading edge. TMDS Input RTD integrates high-speed single link receiver. It can operate up to 165Mhz. Input Capture Window Inside RTD, there are four registers IPH_ACT_STA, IPH_ACT_WID, IPV_ACT_STA & IPV_ACT_LEN to define input capture window for the selected input video on either A or B input port while programmed analog input mode. The horizontal sync (IHS) & vertical sync (IVS) signals are used from the selected port to determine the capture window region.
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IHS IVS
RTD2523/2513
Vertical blanking region (back porch)
IPV_ACT_STA
IPV_ACT_LEN
Input Capture Window
Horizontal blanking region (back porch)
Horizontal blanking region (front porch)
Vertical blanking region (front porch)
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IPH_ACT_STA IPH_ACT_WID
Figure 5 Input Capture Window
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4.2 Output Timing
RTD2523/2513
Display Output Timing The display output port sends single/double pixel data transfer and synchronized display timing to an external device. The display port also support display panel with 6-bit per color, turn on the dithering function to enhance color depth. In single pixel output mode, single pixel data (24-bit RGB) is transferred to display port A on each active edge of DCLK, the rate of DCLK is also equal to display pixel clock. The sync & enable signals are also sent to display port on each active edge of DCLK. Seeing figure13 as below In double pixel output mode, double pixel data (48-bit RGB) is transferred to display port A & B on each active edge of DCLK and the rate of DCLK is equal to half display pixel clock at this moment. The sync & enable signals are also sent to display port on each active edge of DCLK. Seeing figure14 as below.
DCLK DEN DA/RGB
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xxx
rgb0
rgb1
rgb2
rgb3
rgb4
rgb5
DB/RGB
xxx
Figure 6 Single Pixel Mode Display Data Timing
DHCLK DEN DA/RGB DB/RGB
xxx rgb0 rgb2 rgb4 rgb6 rgb8 rgb10
xxx
rgb1
rgb3
rgb5
rgb7
rgb9
rgb11
Figure 7 Double Pixel Mode Display Data Timing
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RTD2523/2513
Display Active Window These registers to define the display active window are showed us below in application with frame buffer. In the case of without frame buffer that means frame sync mode, the definitions of these registers are quiet different from the description below. There are two frame sync modes applied to RTD chip for various applications. Refer to the register description for detailed.
DHS DEN DVS
DV_VS_END Vertical blanking region (back porch) DV_BKGD_STA Background Region DV_ACT_STA
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Display Active Window
Horizontal blanking region (back porch) DV_ACT_END DV_BKGD_END Vertical blanking region (front porch) Horizontal blanking region (front porch)
DV_TOTAL DH_HS_END DH_BKGD_STA DH_ACT_STA DH_ACT_END DH_BKGD_END DH_TOTAL
Figure 8 Display Active Window Diagram
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4.3 Color Processing
RTD2523/2513
Digital color R & G & B independent channel contrast & brightness controls are built in RTD. The contrast control is performed a multiply value from 0/128, 1/128, 2/128... to 255/128 for each R/G/B channel. The brightness control is used to set an offset value from -128 to +127 also for each R/G/B channel.
Scaled RGB
X
+
Gamma Correction
To Dithering
Contrast (0~2) Brightness (-128~127)
Figure 9 Brightness, Contrast & Gamma Correction block diagram
4.4 OSD & Color LUT
Build-In OSD The detailed function-description of build-in OSD, please refer to the application note for RTD embedded OSD.
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Color LUT & Overlay Port The following diagram presents the data flow among the gamma correction, dithering, overlay MUX, OSD LUT and output format conversion blocks.
24
Gamma Correction
24
Dithering
24
Output Format Conversion
Internal OSD Background Color 4
24/48
MUX
4
4
16x24 color look-up table
24
CR38
Figure 10 OSD color look-up table data path diagram
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4.5 Auto-Adjustment
RTD2523/2513
There are two main independent auto-adjustment functions supported by RTD, including auto-position & auto-tracking. The operation procedure is as following; Auto-Position 1. Define the RGB color noise margin (7B,7C,7D): When the value of color channel R or G or B is greater than these noise margins, a valid pixel is found. 2. Define the threshold-pixel for vertical boundary search (7C[1:0]). 3. Define the boundary window of searching (75 ~ 7A) for horizontal boundary search. 4. Start auto-function (7F[0]) . 5. The result can be read from register (80 ~ 87). Auto-Tracking 1. Setting the control-registers (7F) for the function (auto-phase, auto-balance) according to the Control-Table. 2. Define the Diff-Threshold (7E). 3. Define the boundary window of searching (75 ~ 7A) for tracking window. 4. Start auto-function (7F[0]) . 5. The result can be read from register (88 ~ 8B).
4.6 PLL System
Inside the RTD, there are three PLL systems for display clock and ADC sample clock.
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DCLK PLL PLL provides a wide range of user-programmable frequency synthesis options, and the formula as following; The frequency before VCO_Divide must be 50MHz~450MHz. DCLK = Fin * DPM / DPN / VCO_Divide,
Meanwhile, Fin = 24.576MHz, the DPLL_M[7:0] & DPLL_N[5:0] are the 8-bit M & 6-bit N value of DCLK. DPM=DPLL_M[7:0]+2, DPN=DPLL_N[5:0]+2.
Of course, you can force this clock from external oscillators through pins REFCLK for your own applications.
Control Bit1
REFCLK1 Internal CLK CLK PLL
Control Bit0
Figure 11 PLL System Control Diagram Spread-Spectrum function is also build in DCLK to reduce EMI while using TCON. You can control the SSP_I, SSP_W, and FMDIV to fine-tune the EMI.
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4.7 Host Interface
RTD2523/2513
Serial Port: Any transaction should start from asserted the SCS# and stop after de-asserted the SCS#. Within this period, any data are driving by clock rising edge and latched by clock falling edge. The detailed timing diagrams are as following;
R/W : 0 - Write INC : 0 - Address Auto-Inc A0 ~ A7 SCLK SCSB SDIO D0 ~ D7 STOP
A A A A A A A A R IN D D D D D D D D D D D D D D D D D D D D D D D D 0 1 2 3 4 5 6 7 WC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Address
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Data0
Data1
Data2
Address: A0~A7 R/W: Read/Write Mode for Data Phase, 0 -- Write, 1 -- Read INC: Address Auto-Increasing Mode, 0 -- enable auto-increasing, 1 -- disable
Figure 12 Serial Port Write Timing & Data Format
R/W : 1 - Read INC : 1 - Non-Address Auto-Inc A0 ~ A7 SCLK SCSB SDIO STOP D0 ~ D7
Figure 13 Serial Port Read Timing
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Parallel Port:
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After RESET end, the status of pin 9 (TMDS_TST) can be sensed to determine the interface mode: higha parallel port, lowa serial port. Reset end 3.3V SENSE RESET_IN 3.3V TMDS_TST 0V SENSE Figure 15 Serial Port / Parallel Port Select Serial port Parallel port
The 4-bit parallel port works just like our serial port. The biggest difference is that the address part needs 3 clocks but data 2. All the other definitions like "R/W", "INC" and "STOP" are the same with the serial port. The detailed timing diagrams are as following;
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Address SCLK SCSB SDIO [3:0]
SDIO [0] SDIO [1] SDIO [2] SDIO [3]
Data 0
Data 1
Data 2
A [0] A [4] R/W D0 [0] D0 [4] D1 [0] D1 [4] D2 [0] D2 [4] A [1] A [5] A [2] A [6] A [3] A [7] INC D0 [1] D0 [5] D1 [1] D1 [5] D2 [1] D2 [5] X X D0 [2] D0 [6] D1 [2] D1 [6] D2 [2] D2 [6] D0 [3] D0 [7] D1 [3] D1 [7] D2 [3] D2 [7]
1 1 1 1
Figure 16 Parallel Port Timing
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4.8 Reset Output
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We have the RESET_OUT function, and also reserve the RESET_IN function. By the bounding of internal pins we can select three kinds of reset function. First of all is only reset-out, we can output the reset signal to microns, and the micron can reset the RTD by firmware. The second choice is only reset-in, the RTD can be reset by input signal or also firmware. The last is RTD output reset and also reset itself. Noticed that the reset output is positive polarity, the reset in is negative polarity. Besides, the reset output is open-drain pin. The reset function operating voltage is determined by ADC_VDD voltage. The negative threshold voltage is 1.8V at power-on status, but it can be programmed by registers to be 1.8V, 2.0V, 2.2V and 2.4V after power on. The registers are 0xEB [7:6] Die RESET_OU T Die RESET_OU T Die RESET_OU T
RESETB
RESETB
RESETB
Package
RESET_IN
Package
RESET_IN
Package
RESET_IN
Figure 17 Three kinds of RESET function
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For the reset-out function, the characteristics are below: Parameter Symbol Min. Typ. Detection Voltage -Vdet 1.8 2.4 Release Voltage +Vdet 2.6 Delay Time td 50 +3.3V +Vdet -Vdet
Max.
Unit V V ms
+5V
td
RESET_OUT
Figure 18 The RESET_OUT Timing Diagram
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4.9 The Programmable Schmitt Trigger of HSYNC
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To get better waveform of the input HSYNC, we have a programmable Schmitt Trigger circuit. For different HSYNC amplitude and polarity, we can select different setting of the threshold voltage. The Vt+ and the Vt- can be selected by register 0xED. We can select the old mode or the new mode. When using the new mode we can directly determine the positive threshold voltage (1.4V, 1.6V... 2.6V), and we can choose the distance from the Vt+ to determine the Vt- (0.6V, 0.8V, 1.0V, 1.2V). We also can finely tune the voltage by minus 0.1V. For application, we can select different threshold voltage by the polarity of the HSYNC. The control register is 0xED. Input HSYNC Vt
+
Vt-
Output HSYNC
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Figure 18 The Schmitt Trigger Behavior Diagram
4.10 Crystal Frequency Output
RTD can output crystal frequency or half crystal frequency to external MCU to save a crystal device. After power on, RTD latch the state of PLL_TEST2 pin to determine which frequency to output, and the result shows in TCON register address 0x00[0]. 0 is for half of crystal frequency and 1 is for crystal frequency. When power on, crystal frequency output to TCON12 and TCON13. Hence, crystal-in pin of external MCU can connect to TCON12 or TCON13. Firmware can turn off the signal output of other pin, and the control register is in TCON register 0x00[1] and 0x00[2].
4.11 Pin Out Configuration
RTD supports TTL, LVDS and RSDS output interface. After power on, display port is high impedance. Firmware can set its control register in TCON address 0x03[7:6] to select output interface. Refer to Pin Out Diagram for output pin definition. RSDS interface 21
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For dual RSDS output interface, set 2'b11 to "Display Port Configuration" in TCON 0x03[7:6], 1'b1 to "Display 18 bit RGB Mode Enable" in 0x20[4], and 1'b1 to "Display Output Double-Width Pixel Enable" in 0x20[2]. "Display Even/Odd Data Swap" in 0x21[7] can swap even pixel and odd pixel output to RSDS A Port and RSDS B Port. "Display Red/Blue Data Swap" in 0x21[6] can swap red-channel data and blue-channel data. "Display MSB/LSB Data Swap" in 0x21[5] can swap bit order between "bit7, 6, 5, 4, 3, 2" and "bit2, 3, 4, 5, 6, 7". "RSDS Green / Clock Pair Swap" in TCON 0x03[5] can swap three green pair and clock pair order between "G1, G2, G3, CLOCK" and "CLOCK, G1, G2, G3". "RSDS High/Low Bit Swap (data)" in TCON 0x03[1] can swap bit order in one data pair. "RSDS Differential pair PN swap (data)" in TCON 0x03[0] can swap differential positive and negative pin. TCON signal shares pin with parallel access port, PWM, crystal frequency output, video port and DDC channel.
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For single RSDS output interface, set 2'b11 to "Display Port Configuration" in TCON 0x03[7:6], 1'b1 to "Display 18 bit RGB Mode Enable" in 0x20[4], and 1'b0 to "Display Output Double-Width Pixel Enable" in 0x20[2]. "Display Red/Blue Data Swap" in 0x21[6] can swap red-channel data and blue-channel data. "Display MSB/LSB Data Swap" in 0x21[5] can swap bit order between "bit7, 6, 5, 4, 3, 2" and "bit2, 3, 4, 5, 6, 7". "RSDS Green / Clock Pair Swap" in TCON 0x03[5] can swap three green pair and clock pair order between "G1, G2, G3, CLOCK" and "CLOCK, G1, G2, G3". "RSDS High/Low Bit Swap (data)" in TCON 0x03[1] can swap bit order in one data pair. "RSDS Differential pair PN swap (data)" in TCON 0x03[0] can swap differential positive and negative pin. TCON11, 10, 9, 8, 7, 6, 5, 1, 0 use dedicated pin and output to pin 99~107. Video input port also has dedicated pin.
LVDS interface For single/dual LVDS output interface, set 2'b10 to "Display Port Configuration" in TCON 0x03[7:6]. "Display 18 bit RGB Mode Enable" in 0x20[4] determines 6bits or 8bits data output per channel. "Display Output Double-Width Pixel Enable" in 0x20[2] determines one pixel or two pixels output per display clock. "Display Even/Odd Data Swap" in 0x21[7] swap Even port and Odd port data when output double-width pixel enable, and determine output to Even port or Odd port in output single-width pixel mode. "Display Red/Blue Data Swap" in 0x21[6] can swap red-channel data and blue-channel data. Set "Bit-Mapping Table Select" in 0xC2[0] 0 for 8bit LVDS output interface and 1 for 6bit LVDS output interface.
TTL interface For 8bit TTL output interface, set 2'b10 to "Display Port Configuration" in TCON 0x03[7:6], 1'b0 to "Display 18 bit RGB Mode Enable" in 0x20[4]. "Display Output Double-Width Pixel Enable" in 0x20[2] determines one pixel or two pixels output per display clock. "Display Even/Odd Data Swap" in 0x21[7] swaps A port and B port data when output double-width pixel enable, and determine output to A port or B port in output single-width pixel mode. "Display Red/Blue Data Swap" in 0x21[6] can swap red-channel data and blue-channel data. "Display MSB/LSB Data Swap" in 0x21[5] can swap bit order between "bit7, 6, 5, 4, 3, 2, 1, 0" and "bit0, 1, 2, 3, 4, 5, 6, 7". "TTL Display B port Blue [1:0] Location" in TCON register 0x04[4] select where B port 22
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Blue[1:0] output to. If Blue[1:0] output to pin 52&53, RTD must work on serial port access mode. If Blue[1:0] output to pin 46&47, ADC_DDC must be disabled. For 6bit TTL output interface, LSB 2bit of TTL 8bit output is not necessary, and it is used as TCON signal.
TCON Due to the limitation of pin count, TCON shares pins with other signals. Refer to "Display & TCON / Video-8 Port" in the pin definition for TCON configuration. The configuration is in TCON Control Register.
4.12 Display Clock
DPLL DPLL frequency = F_IN * DPM / DPN * Divider. F_IN is input crystal frequency. DPM and DPN is in 0xD1[7:0] and 0xD2[3:0]. Divider is in 0xD2[7:6], and it divide PLL frequency by 1, 2, 4 or 8. According to parameter DPN, you must set LPF Mode in 0xD3[2]. If LPF Mode is 1, the charge pump current, Ich, must be DPM/17.6, while Ich must be DPM/1.67 if LPF Mode is 0. The charge pump current Ich is in 0xD0[0,7:3].
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Offset Frequency The resolution of DPLL frequency from DPM and DPN factor might be not fine enough. Setting DCLK Offset[11:0] can fine tune DPLL close to target frequency. Employing spread spectrum can fine tune DPLL frequency. "Enable DDS Spread Spectrum Output Enable" in register 0x5A[3] allows DDS to output spread spectrum control signal, and "DPLL Spread Spectrum Enable" in 0xD2[5] allows DPLL to receive control signal. "Offset Frequency Direction Induced by Spread Spectrum" in 0xD2[4] controls the direction of offset frequency. "DCLK Offset[11:0]" in 0x9A and 0x9B[3:0] determines the magnitude of offset frequency. Every step of offset frequency is DCLK*2^(-15). In interlaced mode, odd field and even field have different period. Setting 0x9B[6] and 0x9B[4] can enable offset frequency function only in even filed or odd field.
Spread Spectrum Spread spectrum can distribute the radiation energy to a band and reduce EMI. "DCLK Spreading Range" in 0x99[7:4] control spread spectrum range of 0~7.5% (peak-to-peak). "Spread Spectrum FMDIV" in 0x99[3] control spreading frequency 33k or 66kHz.
Fixed the Number of DCLK in a Frame "Enable the Fixed DVTOTAL & Last Line Length" in 0x5A[4] makes there are fixed DVTOTAL and Last Line Length in every frame. Fixed Last Line Length[10:0] is in 0x59 and 23
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0x5A[2:0], and DVTOTAL[10:0] is in register 0x97 and 0x98[2:0]. Output frame is synchronized with input frame by selecting higher-frequency DCLK and lower-frequency DCLK - N*dF according to the position of Display VS leading edge. N is controlled in register 0x99[1:0] and dF is DCLK*2^(-15).
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Registers Description
Reading unimplemented registers will return 0.
Address: 00 ID_REG Bit Mode 7:0 R MSB 4 bits: 1000 product code LSB 4 bits: 0001 rev. code
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Default: 81h Function
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Address: 01 STATUS (Status Register) Default: 00h Function Bit Mode 7 R ADC_PLL Non-Lock: If the ADC_PLL non-lock occurs, this bit is set to "1". 6 R Input VSYNC Error If the input vertical sync occurs within the programmed active period, this bit is set to "1". 5 R Input HSYNC Error If the input horizontal sync occurs within the programmed active period, this bit is set to "1". 4 R Input ODD Toggle Occur If the ODD signal(from SAV/EAV) toggle occurs, this bit is set to "1". 3 R Video-8 Input Vertical Sync Occurs If the YUV input vertical sync edge occurs, this bit is set to "1". 2 R ADC Input Vertical Sync Occurs If the RGB input vertical sync edge occurs, this bit is set to "1". 1 R Input Overflow Status (Frame Sync Mode) If an overflow in the input data capture buffer occurs, this bit is set to "1". 0 R Line Buffer Underflow status (Frame Sync Mode) If an underflow in the line-buffer occurs, this bit is set to "1". Write to clear status.
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Address: 02 HOSTCTRL Bit Mode Function 7 R Display Support 0: XGA (RTD2513/2013) 1: SXGA (RTD2523/2023) 6:5 --Reserved 4 R/W SOG_Mode 0: DC-offset, using POLY R 1: DC-offset, using MOS R 3 --Reserved 2 R/W Power Down Mode Enable 0: Normal 1: Enable power down mode 1 R/W Power Saving Mode Enable (except sync processor & serial port): 0: Normal 1: Enable power saving mode 0 R/W Reset Whole Chip (Low pulse at least 8ms): 0: Normal 1: Enable reset Address: 03 IRQ_CTRL0 (IRQ Control Register 0) Function Bit Mode 7 R/W IRQ (ADC_PLL Non-Lock) 0: Disable the ADC_PLL non-lock error event as an interrupt source 1: Enable the ADC_PLL non-lock error event as an interrupt source 6 R/W IRQ (Input VSYNC Error) 0: Disable the Input VSYNC error event as an interrupt source 1: Enable the Input VSYNC error event as an interrupt source 5 R/W IRQ (Input HSYNC Error) 0: Disable the Input HSYNC error event as an interrupt source 1: Enable the Input HSYNC error event as an interrupt source 4 R/W IRQ (Input ODD Toggle Occur) 0: Disable the Input ODD toggle event as an interrupt source 1: Enable the Input ODD toggle event as an interrupt source 3 R/W IRQ (Video-8 Input Vertical Sync Occurs) 0: Disable the B-port (VGB) Input VSync event as an interrupt source 1: Enable the B-port (VGB) Input VSync event as an interrupt source 2 R/W IRQ (ADC Input Vertical Sync Occurs) 0: Disable the A-port (VGA) Input VSync event as an interrupt source 1: Enable the A-port (VGA) Input VSync event as an interrupt source 1 R/W IRQ (Input Overflow Status) 0: Disable the Input Buffer overflow event as an interrupt source 1: Enable the Input Buffer overflow event as an interrupt source 0 R/W IRQ (Line Buffer Underflow status) 0: Disable the Line Buffer underflow event as an interrupt source 1: Enable the Line Buffer underflow event as an interrupt source
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Default: 02h
Default: 00h
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Input Video Capture
a. Capture Format
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Address: 04 VGIP_CTRL (Video Graphic Input Control Register) Default: 00h Bit Mode Function 7 R/W Vertical Scale-Down Compensation 0: disable 1: enable 6 R/W Horizontal Scale-Down Compensation 0: disable 1: enable 5 R/W Input Test Mode: 0: Normal 1: Video8 input will go through RGB channel, AVS=>IVS, AHS=>IHS, VCLK=>ICLK 4:2 R/W Input Pixel Format 000: From Embedded ADC 001: Reserved 010: Low Speed Input (<60MHz) from Embedded ADC 011: Video-8 from B port (8bits) 100: From Embedded TMDS 101: Reserved 110: Low Speed Input (<60MHz) from Embedded TMDS 111: Reserved 1 R/W Input graphic/video mode 0: From analog input (input captured by `Input Capture Window') 1: From digital input (captured start by `enable signal', but sill stored in `capture window size') 0 R/W Input Video Run Enable 0: No data is transferred 1: Sampling input pixels Address: 05 VGIP_SIGINV (Input Control Signal Inverted Register) Function Bit Mode 7 R/W IVS Sync with IHS Control 0: Enable 1: Disable 6 R/W Input HS Measured Source Select 0: A/B/C port HS 1: HS_RAW/SOG 5 R/W Input CSYNC (HS_RAW or SOG) Inverted Enable 0: Disable 1: Enable 4 R/W Input Video ODD signal invert enable (from EAV) 0: Not inverted (ODD = positive polarity) 1: Inverted (ODD = negative polarity) 3 R/W Input VS Signal Polarity Inverted 0: Not inverted (VS = positive polarity) 1: Inverted (VS = negative polarity) 2 R/W Input HS Signal Polarity Inverted 0: Not inverted (HS = positive polarity) 1: Inverted (HS = negative polarity) 1 R/W Input ENA Signal Polarity Inverted 0: Not inverted (input high active) 1: Inverted (while input low active) 0 R/W Input Clock Polarity 0: Rising edge latched 1: Falling edge latched Default: 00h
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b. Input Frame Window
Address: 06 IPH_ACT_STAL (Input Horizontal Active Start Low) Function Bit Mode 7:0 R/W Input Video Horizontal Active Start -- Low Byte [7:0] Address: 07 IPH_ACT_STAH (Input Horizontal Active Start) Bit Mode Function 2:0 R/W Input Video Horizontal Active Start -- High Byte [10:8] The number of pixel clocks from the leading edge of HS to the first pixel of the active line. IPH_ACT_STA must bigger than 2.
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Address: 08 IPH_ACT_WIDL (Input Horizontal Active Width Low) Bit Mode Function 7:0 R/W Input Video Horizontal Active Width -- Low Byte [7:0] Address: 09 IPH_ACT_WIDH (Input Horizontal Active Width High) Bit Mode Function 2:0 R/W Input Video Horizontal Active Width - High Byte [10:8] This register defines the number of active pixel clocks to be captured. (Horizontal Active Start + Horizontal Active Width) < 2047 This capture width must be increments of four. Address: 0A IPV_ACT_STAL (Input Vertical Active Start Low) Function Bit Mode 7:0 R/W Input Video Vertical Active Start - Low Byte [7:0] Address: 0B IPV_ACT_STAH (Input Vertical Active Start High) Bit Mode Function 2:0 R/W Input Video Vertical Active Start - High Byte [10:8] The number of lines from the leading edge of selected input video VSYNC to the first line of the active window. Address: 0C IPV_ACT_LENL (Input Vertical Active Lines) Function Bit Mode 7:0 R/W Input Video Vertical Active Lines - Low Byte [7:0] Address: 0D IPV_ACT_LENH (Input Vertical Active Lines) Function Bit Mode 2:0 R/W Input Video Vertical Active Lines - High Byte [10:8] This register defines the number of active lines to be captured. Address: 0E IRQ_CTRL1 (IRQ Control Register 1) Default: xxxx_xx00b Bit Mode Function 7 R This bit set to `1' indicates that the read before display SRAM is not ready 6:2 --Reserved. 1 R/W Internal IRQ Enable: 0: Disable these interrupt. 1: Enable these interrupt. The DDC & Status0 IRQ enable will be logically "ORed" together. 0 --Reserved
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Embedded ADC Test Mode
Address: 0F PTNPOS_LO Function Bit Mode 7:0 R/W Test Pattern Position Register [7:0] Assign the test pattern digitized position in pixel.
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Address: 10 PTNPOS_HI Default: 00xx_xxxxb Bit Mode Function 7 R/W TEST (Enable Test Function) 0: Disable 1: Enable, and clear to 0 after latch completed 6 R/W ADC Test Output Enable 0: Disable 1: ADC test data output to ADCOUT [7:0] & ADC_CLK output to BCLK 5:3 R/W Select Color Output To ADC_Test [7:0] 00x: B color 01x: G color 10x: R color 110: Signals (IVS, Coast, IHS, HS_out, IENA , SOG_in, Clamp, IFD_ODD) (MSB-- LSB) 111: Signals (IVS, Coast, IHS, HS_out, Phase Error , SOG_in, FAV4, MSB2 signal) (MSB-- LSB) Test Pattern Position Register[10:8] Assign the test pattern digitized position in pixel. Use PTNPOS to assign the pixel position after HSYNC leading edge that input signal digitized. Each time the PTNPOS is written, the digitized results will be loaded into PTNRD, PTNGD and PTNBD. For test issue, make the input signal a fixed pattern before PTNPOS is written. Then the same digitized output will be got.
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2:0
R/W
Address: 11 PTNRD Function Bit Mode 7:0 R Red Channel Test Pattern Digitized Result. The test pattern digitized result after HSYNC leading edge about PTNPOS pixel. Address: 12 PTNGD Function Bit Mode 7:0 R Green Channel Test Pattern Digitized Result. Address: 13 PTNBD Bit Mode Function 7:0 R Blue Channel Test Pattern Digitized Result.
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Address: 14 INTERNAL FIELD DETECTION Function Bit Mode 7:5 ---Reserved 4 R/W Video mode compensation: 0: disable 1: enable 3 R/W Internal ODD-signal inverse for FS_Delay_Fine_Tuning 0: No invert 1: Invert 2 R/W ODD to Control FS_Delay_Fine_Tuning 0: Disable 1: Enable (FS_Delay_Fine_Tuning must set enable) 1 R/W Internal ODD-signal inverse for video-compensation 0: No invert 1: invert 0 R/W Internal ODD signal selection 0: ODD signal (from EAV) 1: Internal Field Detection ODD signal (Also support under DVI input)
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Default: 00h
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Scaling Up Function
Address: 15 SCALE_CTRL (Scale Control Register) Bit Mode Function 7:6 R/W Fine Tune Delay of coefficient SRAM Access 5:4 R/W Vertical Filter Effect: 00: Filter 1 01: Filter 2 10: Filter 3 11: Filter 4 3:2 R/W Horizontal Filter Effect: 00: Filter 1 01: Filter 2 10: Filter 3 11: Filter 4 1 R/W Enable the Vertical Filter Function: 0: By pass the vertical filter function block 1: Enable the vertical filter function block 0 R/W Enable the Horizontal Filter Function: 0: By pass the horizontal filter function block 1: Enable the horizontal filter function block
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Default: 00h
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Address: 16 HOR_SCA_M (Horizontal Scale Factor Medium) Function Bit Mode 7:0 R/W Bit [11:4] of horizontal scale factor Address: 17 HOR_SCA_H (Horizontal Scale Factor High) Bit Mode Function 7:0 R/W Bit [19:12] of horizontal scale factor This horizontal scale factor includes a 20-bit fraction part to present a horizontal scaled up size over the stream input. For example, for 800-pixel original picture scaled up to 1024-pixel, the factor should be filled in as follows: (800/1024) x 2^20 = 0.78125 x 2^20 = 819200 = C8000h = C8h, 00h, 0h. Address: 18 VER_SCA_M (Vertical Scale Factor Low) Function Bit Mode 7:0 R/W Bit [11:4] of vertical scale factor Address: 19 VER_SCA_H (Vertical Scale Factor High) Bit Mode Function 7:0 R/W Bit [19:12] of vertical scale factor This vertical scale factor includes a 20-bit fraction part to present a vertical scaled up size over the stream input. For example, for 600-line original picture scaled up to 768-line, the factor should be filled in as follows: (600/768) x 2^20 = 0.78125 x 2^20 = 819200 = C8000h = C8h, 00h, 0h. Address: 1A HV_SCA_L (Horizontal/Vertical Scale Factor Low) Function Bit Mode 7:6 R/W Bit [3:2] of horizontal scale factor 5:4 R/W Scale Up Horzontial Latch Delay Fine Tune 3:2 R/W Bit [3:2] of vertical scale factor 1:0 R/W Scale Up Vertical Latch Delay Fine Tune Default: xx00xx00b
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Address: 1B FILTER_CTRL0 (Filter Control Register 1) Bit Mode Function 7:2 R/W Horizontal filter coefficient initial value; default: 110001 1 R/W Enable user defined vertical filter coefficient table 0: disable 1: enable 0 R/W Enable user defined horizontal filter coefficient table 0: disable 1: enable Address: 1C FILTER_CTRL1 (Filter Control Register 2) Bit Mode Function 7:2 R/W Vertical filter coefficient initial value; default: 110001 1 R/W Select User Defined Filter Coefficient Table for Access Channel 0: Horizontal 1: Vertical 0 R/W Enable Filter Coefficient Access 0: disable 1: enable the access channels
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Default: C4h
Default: C4h
Address: 1D FILTER_PORT (User Defined Filter Access Port) Bit Mode Function 7:0 W Access port for user defined filter coefficient table When enable filter coefficient accessing, the first write byte is stored into the LSB(bit[7:0]) of coefficient #1 and the second byte is into MSB (bit[8:11]). Therefore, the valid write sequence for this table is c0-LSB, c0-MSB, c1-LSB, c1-MSB, c2-LSB, c2-MSB ... c63-LSB & c63-MSB, totally 64 * 2 cycles. Since the 128 taps is symmetric, we need to fill the 64-coefficient sequence into table only.
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Address: 1E FS_DELAY_FINE_TUNING (Frame Sync Delay Fine Tuning) Default: 00h Function Bit Mode 7:0 R/W Frame Sync Mode Delay Fine Tune, "00" to disable In Frame Sync Mode #1, this register [7:0] represents output VS delay fine-tuning. For example, it delays the number of (this register[7:0] * 16 + 16) input clocks. Address: 1F STATUS1 (Status1 Register) Function Bit Mode 7 R Line Buffer Overflow Status 1: Line Buffer overflow has occurred since the last status read 6 R Line Buffer Underflow Status 1: Line Buffer underflow has occurred since the last status read 5 R OENA Stop Event Status 1: If the OENA stop event occurred since the last status read 4 R OENA Start Event Status 1: If the OENA start event occurred since the last status read 3 R OVS Start Event Status 1: If the OVS start event occurred since the last status read 2 R IENA Stop Event Status 1: If the IENA stop event occurred since the last status read 1 R IENA Start Event Status 1: If the IENA start event occurred since the last status read 0 R IVS Start Event Status 1: If the IVS start event occurred since the last status read Write to clear status.
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Display Format
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Address: 20 VDIS_CTRL (Video Display Control Register) Default: 00h Bit Mode Function 7 R/W DHS Output Format Select (only available in Frame Sync #1) 0: The first DHS after DVS is active 1: The first DHS after DVS is inactive 6 R/W Display Data Output Inverse Enable 0: Disable 1: Enable (only when data bus clamp to 0) 5 R/W Display Output Force to Background Color 0: Display output operates normally 1: Zoom Filter output is forced to the color as selected by background color 4 R/W Display 18 bit RGB Mode Enable 0: All individual output pixels are full 24-bit RGB 1: All individual output pixels are rounded to 18-bit RGB 3 R/W Frame Sync Mode Enable 0: Free running mode 1: Frame sync mode 2 R/W Display Output Double-Width Pixel Enable 0: Single width pixels are output to the display with every DCLK cycle 1: Double width pixels are output to the display with every DCLK cycle 1 R/W Display Output Run Enable 0: DHS, DVS, DEN & data bus are clamped to "0" 1: Display output normal operation. 0 R/W Display Video Timing Run Enable 0: Display Timing Generator is halted, Zoom Filter halted 1: Display Timing Generator and Zoom Filter enabled to run normally Step to disable output: First set CR20_1=0, set CR20_6 & inverse control, then set CR20_0=0 to disable output. Address: 21 VDIS_SIGINV (Display Control Signal Inverted) Function Bit Mode 7 R/W Display Even/Odd Data Swap: 0: Disable 1: Enable 6 R/W Display Red/Blue Data Swap 0: Disable 1: Enable 5 R/W Display MSB/LSB Data Swap 0: Disable 1: Enable 4 R/W Skew Data Output 0: Non-skew data output 1: Skew data output 3 R/W Display Vertical Sync (DVS) Output Invert Enable: 0: Display Vertical Sync output normal active high logic 1: Display Vertical Sync output inverted logic 2 R/W Display Horizontal Sync (DHS) Output Invert Enable: 0: Display Horizontal Sync output normal active high logic 1: Display Horizontal Sync output inverted logic 1 R/W Display Data Enable (DEN) Output Invert Enable: 0: Display Data Enable output normal active high logic 1: Display Data Enable output inverted logic 0 R/W TMDS_TEST 34 Data Output 0: Disable 1: Enable ( only when TTL mode, 24 bit output ) Default: 00h
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RTD2523/2513
Address: 22 DH_TOTAL (Display Horizontal Total Pixels) Function Bit Mode 7:0 R/W Display Horizontal Total Pixel Clocks: Low Byte[7:0] Address: 23 DH_TOTAL (Display Horizontal Total Pixels) Bit Mode Function 7:3 R/W Frame Sync Mode Fine Tune: Reference 0x31[4] setting 2:0 R/W Display Horizontal Total Pixel Clocks: High Byte[10:8] Determines the number of DCLK cycles in each display line minus 2. (DHS leading edge to DHS leading edge) //**DH_Total (Reg[22],Reg[23], Reg[23]-bit7:3)., Reg[22] Reg[23]** // Address: 24 DH_HS_END (Display Horizontal Sync End) Bit Mode Function 7:0 R/W Display Horizontal Sync End: Determines the width of DHS pulse in DCLK cycles Address: 25 DH_BKGD_STA (Display Horizontal Background Start) Bit Mode Function 7:0 R/W Display Horizontal Background Start: Low Byte [7:0] Address: 26 DH_BKGD_STA (Display Horizontal Background Start) Bit Mode Function 7:3 R The Width Bit [4:0] of Last Line Before Sync in Frame Sync Mode 1 2:0 R/W Display Horizontal Background Start: High Byte [10:8] Determines the number of DCLK cycles from leading edge of DHS to first pixel of Background region. Address: 27 DH_ACT_STA (Display Horizontal Active Start) Function Bit Mode 7:0 R/W Display Horizontal Active Region Start: Low Byte [7:0] Address: 28 DH_ACT_STA (Display Horizontal Active Start) Bit Mode Function 2:0 R/W Display Horizontal Active Region Start: High Byte [10:8] Determines the number of DCLK cycles from leading edge of DHS to first pixel of Active region. Address: 29 DH_ACT_END (Display Horizontal Active End) Function Bit Mode 7:0 R/W Display Horizontal Active Width: Low Byte [7:0] Address: 2A DH_ACT_END (Display Horizontal Active End) Bit Mode Function 2:0 R/W Display Horizontal Active Width: High Byte [10:8] Determines the number of DCLK cycles from leading edge of DHS to the pixel of background region. Address: 2B DH_BKGD_END (Display Horizontal Background End) Bit Mode Function 7:0 R/W Display Horizontal Background end: Low Byte [7:0] Address: 2C DH_BKGD_END (Display Horizontal Background End) Function Bit Mode 7:3 R The Width Bit [9:5] of Last Line Before Sync in Frame Sync Mode 1 2:0 R/W Display Horizontal Background end: High Byte [10:8] Determines the number of DCLK cycles from leading edge of DHS to the start of horizontal blanking. REG_2C[7:3] ®_26[7:3] indicates the width (counted by two pixel) of last line before VSYNC in frame sync mode 1.
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Realtek
RTD2523/2513
Address: 2D DV_TOTAL (Display Vertical Total Lines) Bit Mode Function 7:0 R/W Display Vertical Total: Low Byte [7:0] Address: 2E DV_TOTAL (Display Vertical Total Lines) Bit Mode Function 7:3 R/W Reserved 2:0 R/W Display Vertical Total: High Byte [10:8] In framesync mode, when the line number of Display HS is equal to Display Vertical Total, a status CR3D_7 is set. In FreeRun mode, Display Vertical Total is assigned in {0x98[2:0], 0x97[7:0]}. Address: 2F DV_VS_END (Display Vertical Sync End) Bit Mode Function 7:0 R/W Display Vertical Sync End: Determines the duration of DVS pulse in lines Address: 30 DV_BKGD_STA (Display Vertical Background Start) Function Bit Mode 7:0 R/W Display Vertical Background Start: Low Byte [7:0] Address: 31 DV_BKGD_STA (Display Vertical Background Start) Default: 00000xxxb Bit Mode Function 7 R/W Auto switch when the line number of Display HS is equal to Display Vertical Total 0: Disable 1: Enable 6 R/W Auto switch to (for timing) 0: Disable 1: Free Run 5 R/W Auto switch to (for data) 0: Disable 1: Background 4 R/W Fine Tune Delay Mode Select 0: 0/32 -- 2/32 -- 4/32 -- 6 /32 ~~~ 62/32 1: 0/32 -- 4/32 -- 8/32 --12/32 ~~~ 124/32 3 R Reserved 2:0 R/W Display Vertical Background Start: High Byte [10:8] Determines the number of lines from leading edge of DVS to first line of background region. Address: 32 DV_ACT_STA (Display Vertical Active Start) Function Bit Mode 7:0 R/W Display Vertical Active Region Start: Low Byte [7:0] Address: 33 DV_ACT_STA (Display Vertical Active Start) Default: 000000xxxb Bit Mode Function 7 R/W Auto switch when auto fine tune delay function over max. /min. margin. 0: Disable 1: Enable 6 R/W IRQ Enable 0: Disable auto fine tune delay function over margin occurs as an interrupt source 1: Enable auto fine tune delay function over margin occurs as an interrupt source 5 R Auto fine tune delay function over max. margin status. 4 R Auto fine tune delay function over min. margin status. 3 R/W DVS sync with x4 clock 0: Disable 1: Enable 2:0 R/W Display Vertical Active Region Start: High Byte [10:8] Write to clear status. Determines the number of lines from leading edge of DVS to first line of active region.
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Realtek
RTD2523/2513
Address: 34 DV_ACT_END (Display Vertical Active End) Bit Mode Function 7:0 R/W Display Vertical Active Region End: Low Byte [7:0] Address: 35 DV_ACT_END (Display Vertical Active End) Bit Mode Function 7:4 R Measure al Length Result: Low Byte [3:0] 3 R/W Reserved 2:0 R/W Display Vertical Active Region End: High Byte [10:8] Determines the number of lines from leading edge of DVS to the line of follow background region. Address: 36 DV_BKGD_END (Display Vertical Background End) Bit Mode Function 7:0 R/W Display Vertical Background end: Low Byte [7:0] Address: 37 DV_BKGD_END (Display Vertical Background End) Bit Mode Function 2:0 R/W Display Vertical Background end: High Byte [10:8] Determines the number of lines from leading edge of DVS to the line of start of vertical blanking. Address: 38 IV_DV_LINES (IVS to DVS Lines) Bit Mode Function 7:0 R/W IVS to DVS Lines: (Only for FrameSync Mode) The number of input HS from input VS to output VS.
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Realtek
YUV-to-RGB Control
Address: 39 YUV2RGB (YUV to RGB Control Register) Function Bit Mode 7 R/W SRGB Enable 6 R/W YUV-to-RGB Conversion Mode Selection: 0: YUV422 1: YUV444 5 R/W Enable YUV to RGB Conversion: 0: Disable YVB-to-RGB conversion 1: Enable YUV-to-RGB conversion 4 R/W SRGB SRAM Control 3:2 R/W SRGB Coefficient Write Enable 00: Disable 01: R port 10: G port 11: B port 1:0 R/W U/VROM data latch clock fine tune 01=>10=>00=>11(from fastest to slowest) 00: defalut, each stage=>~0.25ns Address: 3A DIS_TIMING (Display Clock Fine Tuning Register) Bit Mode Function 7 R/W YUV-to-RGB Color Space Conversion Test Mode: 0: Normal 1: Direct output conversion result to display port 6 R/W Internal OSD Port Latch Clock Delay 0: normal 1: 1ns delay 5 R/W Force Display Timing Generator Enable: 0: wait for input VS trigger 1: force enable 4 --Reserved 3 R/W Display Output Clock Coarse Tuning Control: 0: Disable 1: 8ns delay 2:0 R/W Display Output Clock Fine Tuning Control: 000: DCLK rising edge correspondents with output display data 001: 1ns delay 010: 2ns delay 011: 3ns delay 100: 4ns delay 101: 5ns delay 110: 6ns delay 111: 7ns delay
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Default: 00h
Default: 00h
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Address: 3B DIS_TIMING (Display Clock Fine Tuning Register) Default: 00h Bit Mode Function 7 --Reserved 6 R/W PLL_TEST1 input crystal clock (reference to table2. test-pin pair setting) 0: Disable 1: Enable 5:4 R/W DPLL Output Select 00: Select the internal PLL clock source as DPLL output (PWM0 output to REFCLK) 01: Select the external REFCLK clock source as DPLL output 10: Select the internal PLL clock source as DPLL & REFCLK output 11: Select the internal PLL clock source as DPLL output (Video odd/even from EAV output to REFCLK)
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Realtek
3 R/W REFCLK) DCLK Polarity Inverted 0: Non-Inverted 1: Inverted DCLK Output Enable 0: Disable 1: Enable DCLK (on REFCLK pin) Polarity Inverted 0: Non-Inverted 1: Inverted DCLK (on REFCLK pin) Enable 0: Disable 1: Enable
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2
R/W
1
R/W
0
R/W
Address: 3C PE_CTRL Bit Mode Function 7 R/W DDS Tracking Edge 0: HS positive edge 1: HS negative edge 6 R/W PE Measure Enable 0: Disable 1: Enable PE Measurement, clear after finish. 5 R/W FCROM Static Pull-High Control 0: Disable 1: Enable 4:0 R PE Value
Default: 00h
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Address: 3D Status Default: 00h Function Bit Mode 7 R The line number of Display HS is equal to Display Vertical Total, this bit is set to "1". Write to clear status. 6 W PE Max. Measure Clear 0: clear after finish 1: write `1' to clear PE Max. Value 5 R/W PE Max. Measure Enable 0: Disable 1: Enable PE Max. Measurement 4:0 R PE Max Value
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Realtek
RTD2523/2513
Address: 3E DUTY_FINE_TUNE Bit Mode Function 7:4 R/W Internal Display Clock (IDCLK) Duty Fine-tune: (3F_bit1 to enable) 1111 (min fine-tune) a 1110 a 1100 a 1000 a 0000 (max fine-tune) 3:0 R/W Color Processing Clock (CPCLK) Duty Fine-tune: (3F_bit2 to enable) 1111 (min fine-tune) a 1110 a 1100 a1000 a0000 (max fine-tune) Address: 3F DUTY_FINE_TUNE_CTRL Bit Mode Function 7 R/W RSDS data latch Inverted 0: Non-Inverted 1: Inverted 6:4 R/W RSDS data latch Delay 000: 0ns delay 001: 0.5ns delay 010: 1ns delay 011: 1.5ns delay 100: 2ns delay 101: 2.5ns delay 110: 3ns delay 111: 3.5ns delay 3 R/W Internal Display Clock (IDCLK) Delay Enable: 0: Disable. 1: Enable IDCLK delay. 2 R/W Color Processing Clock (CPCLK) Duty Fine-tune Enable: 0: Disable. 1: Enable CPCLK duty fine-tune (setting in 3E_bit3:0) 1 R/W Internal Display Clock (IDCLK) Duty Fine-tune Enable: 0: Disable. 1: Enable IDCLK duty fine-tuner (setting in 3E_bit7:4) 0 R/W Internal Display Clock (IDCLK) Invert. 0: Disable 1: IDCLK invert enable. Default:00h
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Realtek
FIFO Display Window
Address: 40 DRWL_BSU (Display Read Pixel Low Byte Before Scaling-Up) Bit Mode Function 7:0 R/W Display window read width before scaling up: Low Byte [7:0] Address: 41 DRWH_BSU (Display Read Pixel High Byte Before Scaling-Up) Bit Mode Function 2:0 R/W Display window read width before scaling up: High Byte [10:8] Address: 42 DRLL_BSU (Display Read Length Low Byte Before Scaling-Up) Bit Mode Function 7:0 R/W Display window read length before scaling up: Low Byte [7:0] Address: 43 DRLH_BSU (Display Read Length High Byte Before Scaling-Up) Function Bit Mode 2:0 R/W Display window read length before scaling up: High Byte [10:8] Address: 44 sRGB Function Bit Mode 7:0 W When R-port coefficient: RG0, RB0, RG1, RB1, ... RG31, RB31, When G-port coefficient: GR0, GB0, GR1, GB1, ... GR31, GB31, When B-port coefficient: BR0, BG0, BR1, BG1, ... BR31, BG31 total 64 bytes (2' complement : -128~127) s Address: 45 sRGB R-Offset Bit Mode 5:0 R/W (2' complement : -32~31) s
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RTD2523/2513
Function
Address: 46 sRGB G-Offset Bit Mode 5:0 R/W (2' complement : -32~31) s Address: 47 sRGB B-Offset Bit Mode 5:0 R/W (2' complement : -32~31) s R' = Rin[7:0] + R-Offset G' = Gin[7:0] + G-Offset B' = Bin[7:0] + B-Offset Rout = R'[7:0] + GR( G'[7:3] ) + BR( B'[7:3] ) Gout = RG( R'[7:3] ) + G'[7:0] + BG( B'[7:3] ) Bout = RB( R'[7:3] ) + GB( G'[7:3] ) + B'[7:0]
Function
Function
Address: 48 EVENT_STATUS_CONTROL Bit Mode Function 7 R/W Enable Vertical Line Compare Function 0: Disable 1: Enable 6 R/W Gating Vertical Line Compare Function to IRQ 5 R Vertical Line Compare Status (for Polling). Write to clear 4 R/W Select Compare Source: 0: Input Side 1: Display Side 3 -Reserved
Default: 00h
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Realtek
2:0 R/W Select Vertical Line -Low Byte [2:0]
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Address: 49 EVENT_LOCATION Bit Mode 7:0 R/W Select Vertical Line --High Byte [11:3]
Default: 00h Function
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Realtek
SYNC Processor
RTD2523/2513
Address: 4A SYNC_CTRL Default: 00h Bit Mode Function 7 R/W IRQ Enable 0: Disable input sync signal edge occurs as an interrupt source 1: Enable input sync signal edge occurs as an interrupt source 6 R SOG Edge Occurs If the SOG edge occurs, this bit is set to "1". 5 R ADC Input Horizontal Sync Occurs (HS_RAW) If the ADC input horizontal sync edge occurs, this bit is set to "1". 4 R Video-8 Input Horizontal Sync Occurs If the Video-8 input horizontal sync edge occurs, this bit is set to "1". 3 R/W Reserved to 0 Measure VSYNC select 0: The VSYNC chosen by 0x4A [1:0] 1: The VSYNC from de-composite 2 R/W Measure VSYNC Timing Delay 2 clock 0: disable 1: enable 1:0 R/W Measure HSYNC/VSYNC Source Select: 00: RTD300x/RTD20xx original configuration 01: HS_RAW / AVS 10: Video-8 HSYNC / Video-8 VSYNC 11: TMDS HSYNC / TMDS VSYNC Write to clear status. Address: 4B SYNC_CTRL (SYNC Control Register) Bit Mode Function 7 R/W COAST Signal Invert Enable: 0: not inverted 1: inverted 6 R/W COAST Signal Output Enable: 0: disable; 1: enable; 5 R/W HS_OUT Signal Invert Enable: 0: not inverted 1: inverted 4 R/W HS_OUT Signal Output Enable: 0: disable; 1: enable; 3 R/W CLAMP Signal Invert Enable: 0: not inverted 1: inverted 2 R/W CLAMP Signal Output Enable: 0: Disable; 1: Enable 1 R/W Sync-On-Green Enable: 0: Disable; 1: Enable (set "1" to Sync-Mode-Select at the same time) 0 R/W Sync Mode Select: 0: Separate H & V; 1: Composite Sync from HSYNC or Green Address: 4C SYNC_POR (H & V SYNC Polarity Measured Result) Bit Mode Function Default: 00h
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Default: 00h
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Realtek
7 R/W
RTD2523/2513
Safe Mode 0: Normal 1: Safe Mode Enable, mask 1 of 2 IVS. Sync Processor Test Mode 0: Normal 1: Enable Test Mode; (switch 70ns-ck to the time-out & polarity counters) Select HS_OUT Source Signal 0: Bypass HS_RAW 1: Select De-Composite HS out (In Composite mode) Input VSYNC Polarity Indicator 0: negative polarity (high period is longer than low one) 1: positive polarity (low period is longer than high one) Input HSYNC Polarity Indicator 0: negative polarity (high period is longer than low one) 1: positive polarity (low period is longer than high one) Start a HS & VS period / H & V resolution & polarity measurement 0: disable to start a measurement 1: enable to start a measurement, cleared after finished HSYNC & VSYNC Measured Mode 0: HS period counted by crystal clock & VS period counted by HS 1: H resolution counted by input clock & V resolution counted by ENA (Get the correct resolution which is triggered by enable signal, ENA)
6
R/W
5
R/W
3
R
2
R
1
R/W
0
R/W
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Realtek
RTD2523/2513
Address: 4D MEAS_HS_PER (HSYNC Period Measured Result) Bit Mode Function 7:0 R Input HSYNC Period Measurement Result: Low Byte[7:0] Address: 4E MEAS_HS_PER (HSYNC Period Measured Result) Default: 8'bx000xxxx Bit Mode Function 7 R Input HSYNC Period Measurement Result: Over-flow bit 1: Over-flow occurred 6 R/W ODD invert for ODD-Controlled-IVS_delay. 0: Disable 1: Invert 5 R/W ODD-Controlled-IVS_delay Enable 0: Disable 1: Enable 4 R/W Input HSYNC Synchronize Edge 0: Input HSYNC is synchronized by the positive edge of the input clock 1: Input HSYNC is synchronized by the negative edge of the input clock 3:0 R Input HSYNC Period Measurement Result: High Byte[11:8] This result is expressed in terms of crystal clocks. When measured digitally, the result is expressed as the number of input clocks between 2 input HS signals divided by 2. Address: 4F MEAS_VS_PER (VSYNC Period Measured Result) Function Bit Mode 7:0 R Input VSYNC Period Measurement Result: Low Byte[7:0] Address: 50 MEAS_VS_PER (VSYNC Period Measured Result) Bit Mode Function 7 R Input VSYNC Period Measurement Result: Over-flow bit 1: Over-flow occurred 6 R Internal Field Detection ODD toggle happen 5:4 R The number of input HS between 2 input VS. LSB bit [1:0] 3 --Reserved 2:0 R Input VSYNC Period Measurement Result: High Byte[10:8] This result is expressed in terms of input HS pulses. When measured digitally, the result is expressed as the number of input enable signal within a frame. Address: 51 MEAS_HS_HI (HSYNC High Period Measured Result) Function Bit Mode 7:0 R Input HSYNC Period Measurement Result: Low Byte[7:0] Address: 52 MEAS_HS_HI (HSYNC High Period Measured Result) Default: 8'b00xx_xxxx Bit Mode Function 7 R/W HS Recovery in Coast 0: Disable 1: Enable (can turn on when CS or SOG) 6 R/W HSYNC Synchronize source 0: Input HS 1: Feedback HS 3:0 R Input HSYNC Period Measurement Result: High Byte[11:8] This result is expressed in terms of crystal clocks. When measured digitally, the result is expressed as the number of input clocks inside the input enable signal divided by 2. Address: 53 MEAS_VS_HI (VSYNC High Period Measured Result) Bit Mode Function 7:0 R Input VSYNC Period Measurement Result: Low Byte[7:0] Address: 54 MEAS_VS_HI (VSYNC High Period Measured Result) Bit Mode Function 7 R 6-iclk-delay HS level latched by VS rising edge
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Default: 8'bxxx00xxx
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Realtek
6 5 4 R R R/W
RTD2523/2513
HS level latched by VS rising edge HS level latched by 6-iclk-delay VS rising edge Feedback HSYNC Synchronize Edge 0: Feedback HSYNC is synchronized by the positive edge of the input clock 1: Feedback HSYNC is synchronized by the negative edge of the input clock 3 R/W VSYNC Synchronize Edge 0: latch VS by the positive edge of input HSYNC 1: latch VS by the negative edge of input HSYNC 2:0 R Input VSYNC Period Measurement Result: High Byte[10:8] This result is expressed in terms of input HS pulses
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Realtek
Clamping Signal Control
RTD2523/2513
Address: 55 CLAMP_START (Clamp Signal Output Start) Function Bit Mode 7:0 R/W Start of Output Clamp Signal Pulse: Determine the number of input double-pixel between the trailing edge of input HSYNC and the start of the output CLAMP signal. Address: 56 CLAMP_END (Clamp Signal Output End) Function Bit Mode 7:0 R/W End of Output Clamp Signal Pulse: Determine the number of input double-pixel between the trailing edge of input HSYNC and the end of the output CLAMP signal.
Display Data Bus Control (For RSDS type-3)
Address: 57 Display Data Bus Interleaving Line Buffer Length Low Byte Bit Mode Function 7:0 R/W Interleaving Line Buffer Line Bufer: Low Byte [7:0] Address: 58 Display Data Bus Interleaving Line Buffer Length High Byte Bit Mode Function 2 R/W Display Data Bus Interleaving Enable 0: Disable 1: Enable 1:0 R/W Interleaving Line Buffer Line Bufer: High Byte [9:8] Default: 00h
Default: 00h
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Realtek
RTD2523/2513
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Fixed Last Line Length
Address: 59 FX_LST_LN_LNGTH_LSB Bit Mode 7:0 R/W Fixed Last Line Length [7:0] Function
Address: 5A FX_LST_LN_LNGTH_MSB Bit Mode Function 7 R/W New Dithering 0: Disable 1: Enable 6 R/W RSDS_TET_EN 0: Disable 1: Enable 5 R/W SSCG_TST_EN Test Enable 0: Disable 1: Enable(SDMOUT[3:0] will be pass to V8_DATA[3:0]) 4 R/W Enable the Fixed DVTOTAL & Last Line Length Function 0: Disable 1: Enable 3 R/W Enable DDS Spread Spectrum Output Function 0: Disable 1: Enable 2:0 R/W Fixed Last Line Length [10:8]
Default: 0000_0xxxb
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Realtek
Anti-Flicker Control
Address: 5B Bit Mode 7:0 R/W Address: 5C Bit Mode 7 R/W
RTD2523/2513
6
5
4:0
Pixel Threshold Value for Smart Polarity (TH1) Default: 00h Function 2 line Sum of Difference Threshold Value: bit [7:0] Line Threshold Value for Smart Polarity (TH2) Default: 0x000000b Function Measure Dot Pattern over Threshold (depend on 0x00[1]) 1: run. /* Auto: always measure Manual: start to measure, clear after finish */ 0: stop R Dot Pattern Sum of Difference Measure Result 1: over threshold 0: under threshold R/W TCON [7] Polarity one / two Line Toggle Control 1: Auto /* If sum of difference under threshold, TCON [7] will auto switch to "normal " output. If sum of difference over threshold, TCON [7] will auto switch to "original setting" output */. 0: Manual R/W Over Difference Line Threshold Value: bit [4:0]
0x5C[7] & 0x5C[5] anti-flicker `1' & `1' `1' & `0' manual , 0x5C[7]'1', frame, 0x5C[7] clear '0' `0' & `x'
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Color Processor Control
Address: 5D COLOR_CTRL (Color Control Register) Bit Mode Function 7 R/W Dithering Frame Modulation Vertical Enable 0: disable 1: enable 6 R/W Dithering Frame Modulation Horizontal Enable 0: disable 1: enable 5 R/W Enable Access Channel for Dithering Table: 0: disable this channel 1: enable this channel (address should not auto increase) 4 R/W Enable Access Channels for Gamma Correction Coefficient: 0: disable these channels 1: enable these channels (address should not auto increase) 3 R/W Enable Dithering Function: 0: disable the dithering function 1: enable the dithering function 2 R/W Enable Look-Up Table for Gamma Correction Coefficient: 0: disable the look-up table 1: enable the look-up table coefficient 1 R/W Enable Contrast Control Coefficient: 0: disable the coefficient 1: enable the coefficient 0 R/W Enable Brightness Control Coefficient: 0: disable the coefficient Default: 00h
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Realtek
1: enable the coefficient
RTD2523/2513
Brightness Coefficient:
Address: 5E BRI_R_COE (Brightness Red Coefficient) Bit Mode Function 7:0 W Brightness Red Coefficient: Valid range: -128(00h) ~ 0(80h) ~ +127(FFh) Address: 5F BRI_G_COE (Brightness Green Coefficient) Bit Mode Function 7:0 W Brightness Green Coefficient: Valid range: -128(00h) ~ 0(80h) ~ +127(FFh) Address: 60 BRI_B_COE (Brightness Blue Coefficient) Bit Mode Function 7:0 W Brightness Blue Coefficient: Valid range: -128(00h) ~ 0(80h) ~ +127(FFh)
Contrast Coefficient:
Address: 61 CTS_R_COE (Contrast Red Coefficient) Bit Mode Function 7:0 W Contrast Red Coefficient: Valid range: 0(00h) ~ 1(80h) ~ 2(FFh) Address: 62 CTS_G_COE (Contrast Green Coefficient) Function Bit Mode 7:0 W Contrast Green Coefficient: Valid range: 0(00h) ~ 1(80h) ~ 2(FFh) Address: 63 CTS_B_COE (Contrast Blue Coefficient) Function Bit Mode 7:0 W Contrast Blue Coefficient: Valid range: 0(00h) ~ 1(80h) ~ 2(FFh)
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Gamma Correction :
Address: 64 RED_GAMMA_PORT (Red Gamma Table Access Port) Bit Mode Function 7:0 W Access port for red gamma correction table Address: 65 GRN_GAMMA_PORT (Green Gamma Table Access Port) Bit Mode Function 7:0 W Access port for green gamma correction table Address: 66 BLU_GAMMA_PORT (Blue Gamma Table Access Port) Bit Mode Function 7:0 W Access port for blue gamma correction table When enable gamma correction table accessing, total size of coefficient table is 256 bytes for each color respectively. And the input data sequence is c0, c1, c2, ... c255.
Dithering Coefficient:
Address: 67 DITHER_PORT (Dithering Table Access Port) Bit Mode Function 7:0 W Access port for dithering table Old dithering(0x5A[7] = 0): When enable dithering table accessing, total size of coefficient table is 16 * 4 bits for RGB color. And the input data sequence is {c1, c0}, {c3, c2}, ... {c15, c14}. C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
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Realtek
RTD2523/2513
New dithering(0x5A[7] = 1): One dithering sequence table contains 32element, s0, s1, ... , s31. Each element has 2bit to index one of 4 dithering table. Input data sequence is {s3,s2,s1,s0}, {s7,s6,s5,s4}, ... , {s31,s30,s29,s28}. R + (2R+1) * C choose sequence element, where R is Row Number / 2, and C is Column Number / 2. 4 dithering table, 0,1,2,3, is C0 C1 C2 C3 C8 C9 C10 C11 C4 C5 C6 C7 C12 C13 C14 C15
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Realtek
Cyclic-Redundant-Check
Address: 68 OP_CRC_CTRL (Output CRC Control Register) Bit Mode Function 7:2 R/W SRAM Control //111111 (F, I, A, M, G, C) F (bit 7): four-line SRAM I (bit 6): input SRAM A (bit 5): OSD attribute SRAM M (bit 4): OSD font map SRAM G (bit 3): Gamma, Dithering table SRAM C (bit 2): filter coefficient SRAM 1 R/W Enable Full Line buffer: 0: Disable 1: Enable 0 R/W Output CRC Control: 0: Stop or finish (Auto-stop after checked a completed display frame) 1: Start CRC function = X^24 + X^7 + X^2 + X + 1. Address: 69 OP_CRC_BYTE_0 (Output CRC Checksum Byte 0) Bit Mode Function 7:0 R Output CRC-24 bit 7~0 Address: 6A OP _CRC_BYTE_1 (Output CRC Checksum Byte 1) Bit Mode Function 7:0 R Output CRC-24 bit 15~8 Address: 6B OP _CRC_BYTE_2 (Output CRC Checksum Byte 2) Bit Mode Function 7:0 R Output CRC-24 bit 23~16
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RTD2523/2513
Default: FCh
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Realtek
Background color control
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Address: 6C Background color control Bit Mode Function 7:0 R/W Background color RGB 8-bit value There are 3 bytes color select of background R, G, B, and the writing and reading is selected by 0x6D[7:6].
Overlay Control
Address: 6D OVL_CTRL (Overlay Display Control Register) Function Bit Mode 7:6 R/W Background color select (select the writing and reading byte of 0x6c) 00: Red 01: Green 10: Blue 11: X 5:3 R/W Alpha blending level 00:Disable, 001 ~111: 1/8~ 7/8 2 --Reserved 1 R/W Overlay Sampling Mode Select: 0: dual pixels per clock 1: single pixel per clock 0 R/W Overlay Port Enable: 0: Disable 1: Enable Address: 6E OVL_LUT_ADDR (Overlay LUT Address) Function Bit Mode 7 R/W Enable Overlay Color Plate Access: 0: Disable 1: Enable 6 --Reserved 5:0 R/W Overlay 16x24 Look-Up-Table Write Address [5:0] Auto-increment while every accessing "Overlay LUT Access Port". Default: 00h
Default: 00h
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Address: 6F OVL_LUT_PORT (Overlay LUT Access Port) Function Bit Mode 7:0 W Overlay 16x24 Look-Up-Table access port [7:0] Using this port to access overlay color plate which addressing by the above registers. The writing sequence into LUT is {R0, G0, B0, R1, G1, B1, ... R15, G15, and B15} and the address counter will be automatic increment and circular from 0 to 47.
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Realtek
Scale Down Control
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Address: 70 SCALE_DOWN_CTRL (Scale Down Control Register) Default: 00h Bit Mode Function 7 R/W Video 8 Port Input Latch Bus MSB to LSB Swap Control: 0: normal 1: Switched Video8 port MSB to LSB sequence into LSB to MSB 6 R/W Default='0'. When set to `1', vertical scale down is disable in scale down mode 5 R/W Internal ENA (I_ENA) Delay Control: 0: normal; 1: 2ns delay; 4 R/W Internal VS (I_VS) Delay Control: 0: normal; 1: 2ns delay; 3 R/W Internal HS (I_HS) Delay Control: 0: normal; 1: 2ns delay; 2:1 R/W Input Clock Delay Control: 00: Normal 01: 1ns delay 10: 2ns delay 11: 3ns delay 0 R/W Scale down function enable: 0: disable scale down function 1: enable scale down function Address: 71 H_SCALE_DL (Horizontal scale down factor register) Function Bit Mode 7:0 R/W Horizontal Scale Down Factor: Low Byte [7:0] Address: 72 H_SCALE_DH (Horizontal scale down factor register) Bit Mode Function 7:0 R/W Horizontal Scale Down Factor: High Byte [15:8] Registers { H_SCALE_DH, H_SCALE_DL} = (Xi / Xm) x (2^12) truncate. If not truncate, fill minus 1. Meanwhile, Xi = horizontal input width; Xm = horizontal memory write width Address: 73 V_SCALE_DL (Vertical scale down factor register) Function Bit Mode 7:0 R/W Vertical Scale Down Factor: Low Byte [7:0] Address: 74 V_SCALE_DH (Vertical scale down factor register) Bit Mode Function 7:0 R/W Vertical Scale Down Factor: High Byte [15:8] Registers { V_SCALE_DH, V_SCALE_DL} = (Yi / Ym) x (2^12) truncate. If not truncate, fill minus 1 Meanwhile, Yi = vertical input width; Ym = vertical memory write width
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Image Auto Function
Address: 75 H_BOUNDARY_STA_L Bit Mode Function 7:0 R/W Horizontal Boundary Start: Low Byte [7:0] Address: 76 H_BOUNDARY_END_L Bit Mode Function 7:0 R/W Horizontal Boundary End: Low Byte [7:0]
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Address: 77 H_BOUNDARY_HIGH Default: 8'b0xxx_xxxx Bit Mode Function 7 R/W Field_Select_Enable: Auto-Function only active when Even or Odd field. 0: Disable 1: Enable 6:4 R/W Horizontal Boundary Start: High Byte [10:8] //11-bit=2048 3:0 R/W Horizontal Boundary End: High Byte [11:8] //12-bit=4096 Address: 78 V_BOUNDARY_STA_L Function Bit Mode 7:0 R/W Vertical Boundary Start: Low Byte [7:0] //(Invalid when Vertical Auto-Boundary) Address: 79 V_BOUNDARY_END_L Bit Mode Function 7:0 R/W Vertical Boundary End: Low Byte [7:0] //(Invalid when Vertical Auto-Boundary) Address: 7A V_BOUNDARY_HIGH Default: 8'b0xxx_xxxx Function Bit Mode 7 R/W Field_Select: Select Even or Odd field. Active when Field_Select_Enable. 0: Active when ODD signal is "0" 1: Active when ODD signal is "1" 6:4 R/W Vertical Boundary Start: High Byte [10:8] //11-bit //(Invalid when Vertical Auto-Boundary) 3:0 R/W Vertical Boundary End: High Byte [11:8] //12-bit //(Invalid when Vertical Auto-Boundary) Address: 7B RED_NOISE_MARGIN (Red Noise Margin Register) Function Bit Mode 7:2 R/W Red pixel noise margin setting register 1 R/W Even or Odd pixel be measured 0: Even 1: Odd 0 R/W Measure only Even or Odd pixel enable 0: Disable 1: Enable Address: 7C GRN_NOISE_MARGIN (Green Noise Margin Register) Bit Mode Function 7:2 R/W Green pixel noise margin setting register 1:0 R/W Vertical boundary search: 00: 1 pixel over threshold; 01: 2 pixel over threshold 10: 4 pixel over threshold; 11: 8 pixel over threshold Address: 7D BLU_NOISE_MARGIN (Blue Noise Margin Register) Bit Mode Function 7:2 R/W Blue pixel noise margin setting register 1:0 R/W Color Source Select for Detection: 00: B color 01: G color 10: R color Address: 7E DIFF_THRESHOLD Bit Mode 7:0 R/W Difference Threshold Default: 8'bxxxxxx00
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Default: 8'bxxxxxx00
Default: 8'bxxxxxx00
Function
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Next Pixel Current Pixel absolute value 1's com 0 0 1 DFF store max pixel of current and next pixel max DFF if "compare" output 0 compare DFF >=
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>=
0 DFF 1
Enable Substrater Next Pixel Diff_en
_ +
Current Pixel
Inv_en
7F.1 Function Selection 0:Balance / 1:Phase
7F.5 Max/Min Select 0:Min(inv) / 1:Max
7E DifferenceThreshold
7F.6 Diff/Pixel select 0:Pixel-value / 1:Diff
7F.4 Accu/Comp select 0:Comp / 1:Accu
Figure 14 Auto-Tracking Control Block
Address: 7F AUTO_ADJ_CTRL (Auto adjustment control register ) Default: 00h Bit Mode Function 7 R/W Measure Digital Enable Info when boundary search active 0: Normal Boundary Search 1: Digital Enable Info Boundary Search. (The vertical & horizontal, start & end information of external digital signal can be obtained from CR80~87). 6 R/W Accumulation Type 0: Type1 1: Type2 5 R/W Color Max or Min Measured Select: 0: MIN color measured (Only when Balance-Mode, result must be complemented) 1: MAX color measured 4 R/W Accumulation or Compare Mode 0: Compare Mode 1: Accumulation Mode 3:2 R/W Mode Selection (00 is forbidden) 01: Mode1 10: Mode2 11: Mode3 1 R/W Function (Phase/Balance) Selection 0: Auto-Balance 1: Auto-Phase 0 R/W Start Auto-Function Tracking Function: 0: stop or finished 1: start Control Table/ Function Auto-Balance Auto-Phase Type1 Sub-Function Max pixel Min pixel Mode1 Mode2 Mode3 Mode1 Mode2 Mode3 All pixel 7F.6 X X 0 0 0 1 1 1 1 7F.5 1 0 1 1 1 1 1 1 1 7F.4 0 0 1 1 1 1 1 1 1 7F.3 0 0 0 1 1 0 1 1 0 7F.2 X X 1 0 1 1 0 1 1 7F.1 0 0 1 1 1 1 1 1 0 7E X X Th Th Th Th Th Th 0
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Auto-Phase Type2
Accumulation
Table 1 Auto-Tracking Control Table
Address: 80 VER_START_L (Active region vertical start Register) Bit Mode Function
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7:0 R Active region vertical start measurement result: bit[7:0] Address: 81 VER_START_H (Active region vertical start Register) Function Bit Mode 3:0 R Active region vertical start measurement result: bit[11:8] Address: 82 VER_END_L (Active region vertical end Register) Function Bit Mode 7:0 R Active region vertical end measurement result: bit[7:0] Address: 83 VER_END_H (Active region vertical end Register) Function Bit Mode 3:0 R Active region vertical end measurement result: bit[11:8] Address: 84 Bit Mode 7:0 R Address: 85 Bit Mode 3:0 R Address: 86 Bit Mode 7:0 R Address: 87 Bit Mode 3:0 R HOR_START_L (Active region horizontal start Register) Function Active region horizontal start measurement result: bit[7:0] HOR_START_H (Active region horizontal start Register) Function Active region horizontal start measurement result: bit[11:8] HOR_END_L (Active region horizontal end Register) Function Active region horizontal end measurement result: bit[7:0] HOR_END_H (Active region horizontal end Register) Function Active region horizontal end measurement result: bit[11:8]
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Address: 88 AUTO_PHASE_0 (Auto phase result byte0 register) Bit Mode Function 7:0 R Auto phase measurement result: bit[7:0] / The measured value of R or G or B color max or min. (Auto-Balance) Address: 89 AUTO_PHASE_1 (Auto phase result byte1 register) Bit Mode Function 7:0 R Auto phase measurement result: bit[15:8] Address: 8A AUTO_PHASE_2 (Auto phase result byte2 register) Function Bit Mode 7:0 R Auto phase measurement result: bit[23:16] Address: 8B AUTO_PHASE_3 (Auto phase result byte3 register) Bit Mode Function 7:0 R Auto phase measurement result: bit[31:24] Address: 8C IVS_DELAY (Internal Input-VS Delay Control Register) Bit Mode Function 7:0 R/W Input VS delay count by Input HS to reset input data Address: 8D IHS_DELAY (Internal Input-HS Delay Control Register) Bit Mode Function 7:0 R/W Input HS delay count by Input clock Address: 8E ODD_CTRL (ODD Source Control Register) Bit Mode Function 7 R SAV/EAV two-bit error 6 R SAV/EAV one-bit error 5 R/W Auto switch when ADC-PLL non-lock 0: Disable 1: Enable 4 R/W Auto switch when overflow or underflow Default: 00h
Default: 00h
Default: 00h
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0: Disable 1: Enable 3 R/W Decode Video-8 when ADC or TMDS active 0: Disable 1: Enable 2 R/W Input Auto Toggle (TEST) Enable: 0: Disable 1: Enable (DCLK feed to ICLK) (Only works in Video8 port single pixel mode, R & B toggle by ICLK rate, but G toggle by ICLK2 rate) 1 R/W EAV Error Correction Enable in video8 0: Disable 1: Enable 0 R/W 8-bit Random Generator 0: Disable 1: Enable In video8 input format, the bit1 should be the complement of remainder of SAV location clock count/2.
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Address: 8F FCLK (Scale Down Clcok) Fine Tune Bit Mode Function 7:3 -Reserved 3 R/W Select VGIP clock 0: Reference clock 1: DDCSCL 2 R/W Select source of FCLK 0: original setting (default) 1: select ADC_CLK without combinational logic delay 1:0 R/W 0x8F[1] & 0x8F[0] FCLK fine tune 01: slowest 00: typical 1x: fastest
Default: 00h
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Embedded OSD
Address: 90 OSD_ADDR_MSB (OSD Address MSB 8-bit) Bit Mode Function 7:0 R/W OSD MSB 8-bit address Address: 91 OSD _ADDR_LSB (OSD Address LSB 8-bit) Bit Mode Function 7:0 R/W OSD LSB 8-bit address Address: 92 OSD_DATA_PORT (OSD Data Port) Bit Mode 7:0 W Data port for embedded OSD access Refer to the embedded OSD application note for the detailed. Address: 93 OSD_TEST Bit Mode 7:0 R/W Testing Pattern Address: 94 OSD_SCRAMBLE Bit Mode 7 R/W BIST Start 0: stop 1: start (auto clear) 6 R/W BIST Result 0: fail 1: success
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Function
Default: 00h Function
Default: 00h Function
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Embedded Timing Controller
Address: 95 TCON_ADDR _PORT Bit Mode 7:0 R/W Address port for embedded TCON access Address: 96 TCON_DATA _PORT Bit Mode 7:0 R/W Data port for embedded TCON access
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Default: 00h Function
Function
DCLK Spread Spectrum
Address: 97 FIXED_LAST_LINE_MODE_DVTOTAL_LSB Bit Mode Function 7:0 R/W Fixed Last Line Mode DVTOTAL [7:0] Address: 98 FIXED_LAST_LINE_MODE_DVTOTAL_MSB Bit Mode Function 2:0 R/W Fixed Last Line Mode DVTOTAL [10:8] In FreeRun mode, Display Vertical Total is assigned in {0x98[2:0], 0x97[7:0]}. Address: 99 SPREAD_SPECTRUM Function Bit Mode 7:4 R/W DCLK Spreading range (0.0~7.5%) 0000: 0.0% 0001: 0.5% 0010: 1.0% 0011: 1.5% 0100: 2.0% 0101: 2.5% 0110: 3.0% 0111: 3.5% 1000: 4.0% 1001: 4.5% 1010: 5.0% 1011: 5.5% 1100: 6.0% 1101: 6.5% 1110: 7.0% 1111: 7.5% 3 R/W Reserved to 0 Spread Spectrum FMDIV (SSP_FMDIV)//(0) 0: 33K 1: 66K 2 R/W Reserved 1:0 R/W Frequency Synthesis Select (F & F-N*dF) 00~11: N=1~4 df = dclk* 2^(-15) Address: 9A DCLK_FINE_TUNE_OFFSET_ LSB Bit Mode Function 7:0 R/W DCLK Offset [7:0] in Fixed DVTOTAL & Last Line Length Mode Address: 9B DCLK_FINE_TUNE_OFFSET_ MSB Bit Mode Default: 00h
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Default: 00h
Default: 00h Function
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7 6 --R/W
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Reserved Only Even / Odd Field Mode Enable 0: Disable 1: Enable 5 R/W Spread Spectrum Setting Ready for Writing (Auto Clear) 0: Not ready 1: Ready to write 4 R/W Even / Odd Field Select 0: Even 1: Odd 3:0 R/W DCLK Offset [11:8] in Fixed DVTOTAL & Last Line Length Mode The "Spread Spectrum Setting Ready for Writing" (0x9B [5]) means 4 kinds of registers will be set after this bit is set: 1. Spreading range (0x99 [7:4]) 2. Spreading FMDIV (0x99 [3]) 3. DCLK offset setting (0x9A, 0x9B[3:0]) 4. Frequency synthesis select (0x99 [1:0])
Hardware Enhanced Auto Function
Address: 9E HARDWARE_AUTO_PHASE Default: 00h Bit Mode Function 7 R HS_ACT_FLAG 2 R/W Hardware / Software Auto Phase Switch 0: Software 1: Hardware 1:0 R/W Hardware Auto Phase Step 00: Step =1 01: Step =2 10: Step =4 11: Step =8 When hardware auto phase enabled, if the 0x7F [0] is set, then the procedure will start. Every frame the 0x89, 0x8A, 0x8B will be updated by auto-increased phase; the phase will be initially 0 and auto-increased by step setting. The Micron have to read 0x89~8B every frame to get the information. Address: 9F Bit Mode 7 R/W 6:3 R/W 2:1 R/W PLLPHASE (Select Phase to A/D) Function X control 16 phases pre-select Reserved to 00 Phase shift 00: Original phase selected by X, Y, and 16-phase pre-select 01~11: Add 1~3 phase to the Original phase selected by X, Y, and 16-phase pre-select Y control Phase 32 36 40 44 48 52 56 60 [X ^^^^ Y] [0 1000 1] [0 1001 1] [0 1010 1] [0 1011 1] [0 1100 1] [1 1101 0] [1 1110 0] [1 1111 0] Phase 64 68 72 76 80 84 88 92 [X ^^^^ Y] [1 0000 0] [1 0001 0] [1 0010 0] [1 0011 0] [1 0100 0] [1 0101 0] [0 0110 0] [0 0111 0] Phase 96 100 104 108 112 116 120 124 [X ^^^^ Y] [0 1000 0] [0 1001 0] [0 1010 0] [0 1011 0] [0 1100 0] [1 1101 1] [1 1110 1] [1 1111 1] Default: 00h
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0 Phase 0 4 8 12 16 20 24 28
R/W
[X ^^^^ Y] [1 0000 1] [1 0001 1] [1 0010 1] [1 0011 1] [1 0100 1] [0 0101 1] [0 0110 1] [0 0111 1]
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Embedded TMDS
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Address A0: Output Port Enable Default: 6Fh Bit Mode Function 7 R/W Power down TMDS whole function High: Normal Run Low: Power Down 6:5 R/W TMDS_TEST 34 Data Output Select (30 bit over-sampled data, DEN, HS, VS, CLK) 00: Blue channel 01: Green channel 10: Red channel 11: Disable 4 R/W TMDS_TEST 3 DE Output Select 0: Disable 1: 3 channel DE output with CLK (HS, VS be replaced by DE1, DE2) 3 R/W Output control by auto function High: Auto output, Low: Manual. 2:0 R/W Bit 0: Enable Blue output port. Bit 1: Enable Green output port Bit 2: Enable Red output port Address A1: Input Port Enable Default: EFh Bit Mode Function 7 R/W Mcufirst High: disable DDC channel and MCU access only Low: enable DDC channel and MCU access only when DDC is not busy 6 R/W Reserved 5 R/W 1: Original power up sequence, turn on R/G when DE low 128 clocks 0: Turn On R/G channel when DE low 128 clocks and VS rising and falling appears 4 R Chbok: Detect Blue Channel DE low last 128 dclk High: Active, Low: Non-Active
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Input control by auto function High: Auto enable, Low: Manual 2:0 R/W Bit 0: Enable Blue input port. Bit 1: Enable Green input port Bit 2: Enable Red input port Address A2: Analog Performance#1 Bit Mode Function 7 R/W WDmode: Select Watch Dog mode, Low: Analog, High: Digital. 6:5 R/W 00: Auto 10: Watch Dog Pin='1' x1: Watch Dog Pin='0' 4:3 R/W sr[1:0]: The resistor of LPF in PLL. 2:0 R/W si[2:0]: Charge pump current in PLL, Icp=si[2:0]*5u+5u. Address A3: Analog Performance#2 Bit Mode Function 7 R/W anaWDen: Analog watch dog when ckonctrl =1, control pllckon High: Analog & Digital Low: Digital 6 R/W ckon_manual: control pllckon when ckon_ctrl =0, Low: off, High: on. 5 R/W ckonctrl: Low: Manual, High: Auto 4 R/W z0pow: MCU must pull it up after power stable 3 R/W down: When down=0, Z0 is auto set 50 ohm. 2:1 R/W selTST[1:0]: Select the TSTout function of clock port & RD port. 0 R/W ENTST: Enable clock port TSTout pin. 0:Analog to TSTPAD (20k ohm to GND) 1:Digital to TSTPAD (50 ohm to VDD) ENTST::Enable TMDS test singal 0: Disable 1: Enable TMDS power down: set A0[7] & A3[4] to 0 TMDS power save: set A0[7] to 0, A3[4] to 1 Address A4: Analog Performance#3 Bit Mode Function 7:6 Read as "00" 5:4 R/W selTST[1:0]: Select the TSTout pin of Z0_control. 3:0 R/W When down=1, Z0 can be controlled by [3:0] Address A5: Analog_Test_Output_Selection & Digital WD h Bit Mode Function 7:6 R/W selperd: Choose the freq stable time to turn on pllckon Perd Stable Time 00: 16us 32~48us 01: 64us 128~192us 10:256us 512~768us 11: 1ms 2~3ms 5:3 R/W HZTST: Enable TMDS TSTout pin. 0:Enable TSTOUTPAD 1:High impedance STSTPAD 3 R/W
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Default: 8Bh
Default: 26h
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Default: 35h
Default: 9f
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Realtek
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000:TMDS bias to TSTPAD 001:TMDS test singal to TSTPAD 010:D2P (PWM1) singal to TSTPAD 011:P2D (Reserved) singal from TSTPAD (power on latch to select parallel/serial port) 1xx:Force high impedance of TSTPAD selTST[2:0]: Select the TSTout pin to PAD.
2:0
R/W
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Figure 15 TSTOUT Pin Internal Configuration
Address A6: Control Register Function Bit Mode 7 R/W High: CRC check during the next full frame and clear reg. 0xA7~0xA9. Low: After start CRC 6 R CRCdone High: When CRC done Low: When set 0xA6[7] 5 R/W Indicate VSYNC Polarity Mode: High: manual, decided by 0xA6[0] Low: auto, indicate by 0xA6[4] 4 R Indicate VSYNC Polarity High: Negative Low: Positive 3 R/W Reserved to 0 2 R/W Reserved 1 R/W Always PRE-charge: Default: 08h
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High: Enable, Low: Disable 0 R/W Reserved Address A7: CRC Output Byte_0 Default: XX Bit Mode Function 7:0 R CRC output bit 7~0 Cleared when 0x04[2] is set. Address A8: CRC Output Byte_1 Default: XX Bit Mode Function 7:0 R CRC output bit 15~8 Address A9: CRC Output Byte_2 Default: XX Bit Mode Function 7:0 R CRC output bit 23~16 Address AA: DB Test Mode Default: 00h Bit Mode Function 7 R/W Reserved to 0 6 R Reserved 5 R/W TMDS test output enable (only when ADC test output disable) High: TMDS test data output to VIDEO8 PAD Low: Disable 4 R/W Shwp: show write pointer High: show wp at VIDEO8 [5:0] wp decided by wpsel[1:0] Low: other bits make decision 3 R/W Shctl: High: bypass CTL3~0 to VIDEO8 [3:0] Low: VIDEO8[3:0]=[0000] 2 R/W f25tst: After the rising edge first full cycle data and hold system when TI,TO,TCK active, data could be shift out by the order R30bit 0~29,R12bit 0~11,G,B; where 12bit and 30bit data decided by f25sel Z0TST<0>= VIDEO8 [2] Z0TST<1>= VIDEO8 [3] TCK2= AVS, decided by 0xAB[7] TO = VIDEO8 [5], TI = DDCSDA, TCK = DDCSCL, 1 R/W shauth: High: show authst, authkm, authdone to VIDEO8[2:0] Low: VIDEO8[2:0]={000} 0 R/W shclk: High: show crystal, fbakdiv5, findiv2, dclk (dclk/2) to VIDEO8[3:0] Low: VIDEO8[3:0]=[0000] Address AB: DVI_REG_TEST Default: 00h Bit Mode Function 7 R/W tck_mode: High: TCK2 mode Low: Original 6:4 R/W f25sel: Decision latched data of F2x5FIFOT: check 12bit 30bit 000 [11:0] lat0 29:0 001 [23:12] lat1 29:0 010 [47:36] lat3 59:30 011 [59:48] lat4 59:30 10x [29:24] lat2 29:0 11x [35:30] lat2 59:30
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3 2:1 R/W R/W
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Reserved wpsel: Display selection of write pointer of TMDS, 00: wp=6'h00, 01: wp of blue channel 10: wp of green channel 11: wp of red channel 0 R/W dclkdiv: Low: out dclk when shwp=0,shck=1 to VIDEO8[0] High: dclk/2 Address AC: Pattern Comparator Default: 90h Bit Mode Function 7 R/W Calibration of FIFO write pointer after Vsync High: Enable calibration, Low: Disable 6 R/W Calibration write pointer Vsync edge select High: Falling, Low: Rising 5 R/W Hsync edge select after Vsync calibrate write pointer High: Falling, Low: Rising 4 R/W Clock delay select after Hsync calibrate write pointer High: Enable delay 5 clock Low: Disable 3 R/W Calibration of FIFO write pointer and boundary detection after falling DE High: Enable calibration, Low: Disable 2 R/W pertst: High: start to do pixel error rate test wait for matched pattern Low: stop PERT and clear numerr and perten 1 R/W pertmode: High: PN code PERT Low: Half clock PERT 0 R perten: High: matched pattern found PERT(Pixel Error Rate Test) enable Low: clear by pertst reset Address AD: Pixel Error Rate Low Byte Default: 00h Bit Mode Function 7:0 R Numerr low byte: Total count of pixel error Address AE: Pixel Error Rate High Byte Default: 00h Bit Mode Function 7:0 R Numerr high byte: Total count of pixel error Address AF: DVI_CTRL1 Default: 00h Bit Mode Function 7 R/W Reserved 6:4 R If Red/Green/Blue FIFO overflow or underflow, These will set `1', clear `0' after read. 3 R/W Reserved 2 R/W OCLK divide 2: High: Enable Low: Disable 1:0 R/W Reserved F25CK Delay: 00 : 2ns 01 : 2.7ns 10 : 3.7ns 11 : 4.7ns delay clock 1x from analog Address B0: TMDS CTL0~3 Signal Status Default:30h
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Bit 7:4 3 2 1 0 Mode R/W R R R R Function Reserved TMDS internal CTL3 signal status TMDS internal CTL2 signal status TMDS internal CTL1 signal status TMDS internal CTL0 signal status
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Address B1: Reserved Bit Mode 7:0 R/W Reserved Address B2: Device Key BIST Pattern Bit Mode 7 R/W Reserved 6:0 W BIST Pattern Input Address B3: TMDS_TEST_MODE_1 Bit Mode 7:6 R/W Phase select Mode BLUE 00: Original 01: Fix middle 10: Fix back 11: Fix front 5:4 R/W Phase select Mode GREEN 3:0 R/W Continuous Change 0000: 1 ~ 1111: 16
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Default: 00h Function
Function
Default: 00h Function
Address B4: TMDS_TEST_MODE_2 Bit Mode 7:6 R/W Phase select Mode RED 5:4 R/W Data Picking Select BLUE 0x: Middle 10: Front 11: Back 3:2 R/W Data Picking Select GREEN 1:0 R/W Data Picking Select RED Address B5: Reserved Address B6: Reserved Bit Mode 7:0 R/W Reserved Address B7: Reserved Bit Mode 7:0 R/W Reserved Address B8~BF Reserved
Default: 00h Function
Default: 00h Function
Function
DVI DDC Channel
(Refers to the VESA "Display Data Channel Standard" for detailed, DVI channel only support DDC2B) Address: BC DDC_ENABLE (DDC Channel Enable Register) Default: 00h Bit Mode Function 7:5 R/W DDC Channel Address Least Significant 3 Bits
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4 3 R R/W (The default DDC channel address MSB 4 Bits is "A") DDC Write Status (for external DDC access only) It is cleared after write. DDC SRAM Write Enable (for external DDC access only) 0: Disable 1: Enable DDC Debounce Enable 0: Disable 1: Enable (with crystal / 4) DDC Channel RAM Size 0: 128 bytes 1: 256 bytes DDC Channel Enable Bit 0: MCU access Enable 1: DDC channel Enable
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2
R/W
1
R/W
0
R/W
Address: BD DDC_INDEX (DDC SRAM R/W Index Register) Bit Mode Function 7:0 R/W DDC SRAM Read/Write Index Register [7:0] The DDC channel index register will be auto increased one by one after each read or write cycle. Address: BE DDC_ACCESS_PORT (DDC Channel ACCESS Port) Function Bit Mode 7:0 R/W DDC SRAM Read/Write Port ** The DDC function can still work when Power_Down & Power_Save. ** After reset, the register will be set to default value, but the SRAM will keep original data.
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Control for LVDS
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Address: C0 LVDS_CTRL0 Default: 00h Bit Mode Function 7 R/W Power down PLL 0: Power down 1: Normal 6 R/W Power down even-port 0: Power down 1: Normal 5 R/W Power down odd-port 0: Power down 1: Normal 4 R/W Enable PLL test signal to PLLTST 0: Disable 1: Enable 3 R/W Select PLLtest-pin 0: Fbak 1: Fin 2:1 R/W Watch Dog Model 00: Enable Watch Dog 01: Keep PLL VCO = 1V 1x: Disable Watch Dog 0 R Watch Dog Control Flag 0: Disable watch dog 1: Reset PLL and set VCO = 1V Address: C1 LVDS_CTRL1 Default: 04h Function Bit Mode 7 R/W TTL_TST_EN 0: Disable 1: Enable 7:4 --Reserved 3 R/W Pin connected with capacitors (2.6pF) 0: yes 1: no 2:0 R/W RSDS / LVDS Output Common Mode (100) For TTL_TST_EN test mode, we use the video port as input, then we could not test the signal output from video port. In 8 bit TTL mode, if set to 1, these signals will be redirect to other pins, and the test fault coverage will be higher.... Address: C2 LVDS_CTRL2 Default: 52h Function Bit Mode 7:6 R/W SBGL [1:0]: Bandgap Voltage (~1.2V) 5:3 R/W SIL [2:0]: PLL charge pump current (I=5uA+5uA*code) 2:1 R/W SRL [1:0]: PLL resistor 0 R/W BMTS: Bit-Mapping Table Select High: Table 2 Low: Table 1 TCLK+ LVDS Even A Even B Even C Even D Odd A Bit 1 ER1 EG2 EB3 ER7 OR1 Bit 0 ER0 EG1 EB2 ER6 OR0 Bit 6 EG0 EB1 DEN*6 RSV*7 OG0 Bit 5 ER5 EB0 VS*5 EB7 OR5 Bit 4 ER4 EG5 HS*5 EB6 OR4 Bit 3 ER3 EG4 EB5 EG7 OR3 Bit 2 ER2 EG3 EB4 EG6 OR2 Bit 1 ER1 EG2 EB3 ER7 OR1 Bit 0 ER0 EG1 EB2 ER6 OR0 Bit 6 EG0 EB1 DEN*6 RSV*7 OG0 Bit 5 ER5 EB0 VS*5 EB7 OR5
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Odd B Odd C Odd E OG2 OB3 OR7 OG1 OB2 OR6 OB1 DEN*2 RSV*3 OB0 VS*1 OB7 OG5 HS*0 OB6 OG4 OB5 OG7 OG3 OB4 OG6 OG2 OB3 OR7
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OG1 OB2 OR6 OB1 DEN*2 RSV*3 OB0 VS*1 OB7
TABLE 1 Bit-Mapping 6bit(5~0)+2bit(7~6)
TCLK+ LVDS Even A Even B Even C Even D Odd A Odd B Odd C Odd E Bit 1 ER3 EG4 EB5 ER1 OR3 OG4 OB5 OR1 Bit 0 ER2 EG3 EB4 ER0 OR2 OG3 OB4 OR0 Bit 6 EG2 EB3 DEN*6 RSV*7 OG2 OB3 DEN*2 RSV*3 Bit 5 ER7 EB2 VS*5 EB1 OR7 OB2 VS*1 OB1 Bit 4 ER6 EG7 HS*5 EB0 OR6 OG7 HS*0 OB0 Bit 3 ER5 EG6 EB7 EG1 OR5 OG6 OB7 OG1 Bit 2 ER4 EG5 EB6 EG0 OR4 OG5 OB6 OG0 Bit 1 ER3 EG4 EB5 ER1 OR3 OG4 OB5 OR1 Bit 0 ER2 EG3 EB4 ER0 OR2 OG3 OB4 OR0 Bit 6 EG2 EB3 DEN*6 RSV*7 OG2 OB3 DEN*2 RSV*3 Default: 80h Bit 5 ER7 EB2 VS*5 EB1 OR7 OB2 VS*1 OB1
TABLE 2 Bit-Mapping 6bit(7~2)+2bit(1~0)
Address: C3 LVDS_CTRL3 Bit Mode Function 7:6 R/W E_RSV_s: even port reserve signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [3] 00: PWM_0 5:4 R/W E_DEN_s: even port data enable signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [2] 00: E_DEN (DENA) 3:2 R/W E_VS_s: even port VS signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [1] 00: E_VS (DVS) 1:0 R/W E_HS_s: even port HS signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [0] 00: E_HS (DHS) Address: C4 LVDS_CTRL4 Bit Mode Function 7:6 R/W O_RSV_s: odd port reserve signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [4] 00: PWM_1 5:4 R/W O_DEN_s: odd port data enable signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [2] 00: O_DEN (DENA) 3:2 R/W O_VS_s: odd port VS signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [1]
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Default: 80h
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Realtek
1:0 R/W 00: O_VS (DVS) O_HS_s: odd port HS signal select 11: Alawys `1' 10: Alawys `0' 01: TCON [0] 00: O_HS (DHS) LVDS_CTRL5
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Address: C5 Bit Mode 7:4 R/W Bias Generator Adjust (0110) 3 R/W Bandgap of LVDS/RSDS Power on 0: Off 1: On 2:0 R/W STSTL [2:0]: select test attribute 000: High Impedance 001: VOCME 010: VBG 011: 60uA (20K ohm to GND) 1xx: TSTPLL (50 ohm to VDD)
Default: 60h Function
Power save & power down: set C0[7:5] to 0, C5[3] to 0
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Realtek
Control for PLL DIV
Address: C8 PLL_DIV_CTRL0 Bit Mode Function 7:6 Reserved. --5 R/W DDS Reset Enable 0: Normal function 1: DDS circuit' reset will be asserted, for test only s 4 R/W Test Mode: (for production test) 0: Normal 1: Test Mode 3 R/W HS output synchronized by 0: phase 16 1: phase 0 2:1 R/W Phase error detect mode 00: zero mode (FB is aligned to nedegde of Fav) 01: 1 mode (FB is aligned to posedge of Fav) 1x: direct mode (FB is direct to PFD) 0 R/W Clock select for DIV 0: phase 0 (phase-0 of PLL2) 1: internal CLK (Fav) Address: C9 I_CODE_L Bit Mode Function 7:5 R/W I_Code [7:5] For old I or New_I mechanism depending on 0xc9[0] & 0xc9[4] 4 R/W I_Code [4] / I-code control mechanism 0: new linear mode, PE*(2+NEW_I[12])*2^(NEW_P+2) 1: old mode, P-code = P-code_2011 - 1 3:2 R/W I_Code [3:2] / P-code protection mode 00 => No protection 01 => 1 bit protection 10 => 2 bits protection 11 => 3 bits protection 1 R/W I_Code [1] / P-code mapping curve 0: choose the new P-code mapping curve 1: choose the old P-code mapping curve 0 R/W I_Code [0] /I-code multiplication factor 0: choose the new I-code multiplication factor = NEW_I[9:5] (PE)*(2+NEW_I[13])* 2^(NEW_I[9:5]+2) 1: choose the old I-code multiplication factor Address: CA Bit Mode 7:6 R/W 5 R/W 4 R/W 3 R/W 2 R/W I_CODE_M Function
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Default: 00h
Default: 61h
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Default: 18h
1:0
R/W
I_Code [15:14] I_Code [13] / I_code calibrated setting I_Code [12] / P_code calibrated setting I_Code [11] / Overwrite 0 to 1 return a new PFD calibrated value. I_Code [10] / 0: Old PFD 1: New PFD I_Code [9:8] / For old I or New_I mechanism depending on 0xc9[0] & 0xc9[4] Default: 18h Function
Address: CB P_CODE Bit Mode 7 Reserved ---
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Realtek
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6:5 R/W I_Code[17:16]//00 4:0 R/W P_Code[4:0] //0x18 N P_Code=2 * ; N is bit number, N=32 ; is ratio of phase error correction. Default =2-7 , P_Code=225 ; P[4:0]=25-1=24=5'h18 ; P[4:0] can not bigger than 5'h1F-6=5'h19. When phase-error is too large, P_Code will enlarge to at most 64 times automatically. I_Code=(*2N)/PLLDIV ; N is bit number, N=32 ; is ratio of frequency error correction. Default =2-9, PLLDIV=1344, I_Code=6241=18'h01861. must be smaller than . Address: CC PLLDIV_HI Bit Mode Function 3:0 R/W PLL Divider Ratio Control. High-Byte [11:8]. Default: 05h
Address: CD PLLDIV_LO Default: 3Fh Bit Mode Function 7:0 R/W PLL Divider Ratio Control. Low-Byte [7:0]. This register determines the number of output pixel per horizontal line. PLL derives the sampling clock and data output clock (DCLK) from input HSYNC. The real operation Divider Ratio = PLLDIV+1 The power up default value of PLLDIV is 053Fh(=1343, VESA timing standard, 1024x768 60Hz, Horizontal time). The setting of PLLDIV must include sync, back-porch, left border, active, right border, and front-porch times. Control-Register CC & CD will filled in when Control-Register CD is written. Address: CE PFD Calibrated Results Function Bit Mode 5:0 R/W PFD Calibrated Results This register determines the number of output pixel per horizontal line. PLL derives the sampling clock and data output Address: CF
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Reserved
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Realtek
Phase Lock Loop
Address: D0 DPLL_CRNT (DPLL Charge Pump Current Register) Bit Mode Function 7:3 R/W Charge Pump Current Idch [4:0] 2 R Watch Dog Status 0: Normal 1: Abnormal 0 R/W Charge Pump Current Idch [5] I = 2.5u + D0 [3]*2.5u + D0 [4]*5u + D0 [5]*10u + D0[6]*20u + D0[7]*30u (A) Ich (Charge pump current) = I * ( D0[0] + 1) / 2 Address: D1 DPLL_M (DPLL M Divider Register) Bit Mode 7:0 R/W DPM value - 2
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Default: 00010xx0b
Default: 01111101b Function
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Address: D2 DPLL_N (DPLLN Divider Register) Default: 00001010b Bit Mode Function 7:6 R/W DPLL Output Divider (00a 1, 01a 1/2, 10a1/4, 11a1/8) // (01) 5 R/W DPLL Spread Spectrum Enable 0: Disable 1: Enable 4 R/W Offset Frequency Direction Induced by Spread Spectrum 0: Upward 1: Downward 3:0 R/W DPN value - 2 DPLL must be twice DCLK frequency and max DPLL frequency is 320MHz. Assume DPLL_M=0x7D, DPM=0x7D+2=127; DPLL_N=0x0A, DPN=0x0A+2=12; Divider=1/4, F_IN = 24.576MHz. F_DPLL = F_IN x DPM / DPN x Divider = 24.576 x 127 / 12 / 4 = 65.024MHz. If LPF_Mode = 1, suppose DPM=110, DPN = 12, Ich = Idch[000100] = 6.25uA, DPLL=225MHz, then DPM / Ich =17.6. Please keep the ratio as constant. If LPF_Mode = 0, suppose DPM=46, DPN = 5, Ich = Idch [101010] =27.5uA, DPLL=226MHz, then DPM / Ich = 1.67. Please keep the ratio as constant. Address: D3 DPLL_FILTER (Loop Filter Control Register) Function Bit Mode 7 R/W DPLL Output Enable 0: Enable 1: Disable 6:3 R/W Reserved 2 R/W LPF Mode 0: DPN <= 5 1: DPN <= 16 1:0 R/W Loop Filter Resistance Control 00: 16K (LPF Mode = 0), 46K (LPF Mode = 1) 01: 18K (LPF Mode = 0), 53K (LPF Mode = 1) 10: 20K (LPF Mode = 0), 60K (LPF Mode = 1) 11: 22K (LPF Mode = 0), 67K (LPF Mode = 1) Address: D4 DPLL_SSP (Spread Spectrum Control Register) Bit Mode Function 7:6 R/W Watch Dog State Setting 00: WD active 01: WD take over 1x: WD sleep 5:4 R/W Watch Dog Voltage Setting Default: xx10_1111b
Default: 0000011xb
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Realtek
00: 0.8V 01: 1.3V 10: 1.8V 11: 2.3V Reserved Test-Pin 2 Input/Output Switch 0: Output 1: Input Test-Pin 1 Input/Output Switch 0: Input 1: Output Reserved
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3 2
R/W R/W
1
R/W
0
R/W
Address: D6 PLL1_CTRL (PLL1 Control Register) Bit Mode Function 7:4 R/W Charge Pump Current (5uA ~ 80uA)//(0001) 3 R PLL1 Status 0: Normal 1: Abnormal 2 ---Reserved 1 R/W MSB Clock Stop//(1) 0: Stop (for Test) 1: Normal Run 0 R/W PLL1 Power Down//(0) 0: Power Down 1: Normal Run Address: D7 PLL1_M (M Parameter Register) Bit Mode 7:0 R/W P1M value - 2
Default: 0001xx10b
Default: (0Bh) Function
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Address: D8 PLL1_N (N Parameter Register) Default: 03h Bit Mode Function 5:0 R/W P1N value - 2 Assume PLL1_M=0x0B, P1M=0x0B+2=13; PLL1_N=0x03, P1N=0x03+2=5; F_IN = 24.576MHz. F_PLL1 = F_IN x P1M / P1N = 24.576 x 13 / 5 = 63.8976MHz If the target frequency is F_ADC, the constraint of F_PLL1 is (15/16)*F_ADC < F_PLL1 < F_ADC Address: D9 PLL1_FILTER (Loop Filter Control Register) Default: 6Fh Function Bit Mode 7:6 R/W BandGap Voltage Select (Default = 01). 5:3 R/W Loop Filter Resistance Control (1Kohm ~ 8Kohm). 6Kohm is preferred.(101) 2:0 R/W Loop Filter Capacitance Control (20pF ~ 160pF). 160pF is preferred.(111)
Test-Pin In/Out Pair select DA[3:1] 0(In) xxx Tp1 1(Out) 000 1(Out) 001 1(Out) 010 1(Out) 011 1(Out) 100 1(Out) 101 1(Out) 110 1(Out) 111 xxx x x
Signal lin1 Poweronchk2 LOCK1 cko fav3v ckk2bb vopp8 BVS IRQ
Description lin1 is sent to ADC by setting (Reference to 0xDD[7:6]) Power-on-reset signal (external) PLL1's clock detector (0 is normal) PLL's ADC output clock fav signal (from DDS) PLL2's VCO output clock PLL1's VCO output clock Video8 VS from EAV Low active Crystal signal input (3B[6]=1)
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Realtek
Test-Pin In/Out Pair select DA[3:1] Tp2 1(In) xxx 0(Out) 000 0(Out) 001 0(Out) 010 0(Out) 011 0(Out) 100 0(Out) 101 0(Out) 110 0(Out) 111 Signal Xtal F. Select poweron chk1 GND LOCK2 HSFB HSFB GND BHS GND Description
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Power on latch to determine the Xtal output frequency Power-on-reset signal (internal) DPLL's clock detector (0 is normal) PLL2's clock detector (0 is normal) (From DDS) (From DDS) PLL' GND s Video8 HS from SAV/EAV PLL' GND s
Table 2 Test-Pin Pair Setting
Address: DA PLL2_CTRL (PLL2 Control Register) Bit Mode Function 7:4 R/W Charge Pump Current (5uA ~ 80uA)//(0001) 3:1 R/W Select 1 pair of 8 pairs signal to testpin (default = 000). 0 R/W PLL2 Power Down //(0) 0: Power Down (default) 1: Normal Run Default: 10h
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Address: DB PLL2_M (M Parameter Register) Default: 0Ah Function Bit Mode 7:0 R/W P2M value - 2 Address: DC PLL2_N (N Parameter Register) Default: 04h Bit Mode Function 7 R PLL2 Status 0: Normal 1: Abnormal 5:0 R/W P2N value - 2 Assume PLL2_M=0x0A, P2M=0x0A+2=12; PLL2_N=0x04, P2N=0x04+2=6; F_IN =65 MHz . F_PLL2 = F_IN x P2M x 2 / P2N /2 = 65 x 12 x 2 / 6 / 2 = 130 MHz the constraint of F_PLL2 is that P2N =(int)(F_IN / 10) Address: DD PLL2_FILTER (Loop Filter Control Register) Default: EFh Bit Mode Function 7:6 R/W Select CLK to A/D from 00: internal PLL (PLL2 phase-select output) 01: inverse internal PLL (PLL2 phase-select output) 10: test-pad clock (PLL_TEST1 input) 11: internal x2 PLL (PLL2 phase-select output) (Reference to 0xEA[2]) 5:3 R/W Loop Filter Resistance Control (1Kohm ~ 8Kohm). 6Kohm is preferred.(101) 2:0 R/W Loop Filter Capacitance Control (20pF ~ 160pF). 160pF is preferred.(111) Address: DF Reserved Bit Mode 7:0 R/W Reversed Default: 1000_0xx0b Function
Embedded ADC
Address: E0 REDGAIN Bit Mode 7:0 R/W RED Channel Gain Adjust Address: E1 GRNGAIN Bit Mode Function
Function
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Realtek
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7:0 R/W Green Channel Gain Adjust Address: E2 BLUGAIN Bit Mode Function 7:0 R/W Blue Channel Gain Adjust Adjust the full-scale input range that corresponds to the maximum digital 8-bit binary output. Setting REDGAIN to 0 corresponds to an input full-scale range of 0.5V, and 255 adjust the input full-scale range to 1.0 V. That means the GAIN setting will change the LSB resolution. Increasing the gain results in larger input range, and less contrast effect is visible. Address: E3 REDOFST Bit Mode Function 7:0 R/W Red Channel Clamp Offset FFh : clamp Vin+128*(Vfs/256) in back porch period as code 00h. 80h : clamp Vin in back porch period as code 00h. 00h : clamp Vin-128*(Vfs/256) in back porch as code 00h. Address: E4 GRNOFST Bit Mode Function 7:0 R/W Green Channel Clamp Offset FFh : clamp Vin+128*(Vfs/256) in back porch period as code 00h. 80h : clamp Vin in back porch period as code 00h. 00h : clamp Vin-128*(Vfs/256) in back porch as code 00h. Address: E5 BLUOFST Function Bit Mode 7:0 R/W Blue Channel Clamp Offset FFh : clamp Vin+128*(Vfs/256) in back porch period as code 00h. 80h : clamp Vin in back porch period as code 00h. 00h : clamp Vin-128*(Vfs/256) in back porch as code 00h. Vfs: Input full-scale voltage depends on REDGAIN setting, Vin: Input channel signal, Vbp: Vin in back porch period This register is used to adjust the input clamp level. One LSB offset (=Vfs/256) equals one LSB change in ADC output. Increasing the offset setting results in less brightness. Be careful that input full-scale voltage depends on GAIN setting, so the LSB offset step will be increased when increasing the GAIN setting. Address: E6 ADC_CTRL Function Bit Mode 7:3 R/W SOG Reference Control //(10000) 2 R/W ADC R-Channel Power Down (SOG Circuit always enable) //(0) 0: ADC Power Down 1: Normal 1 R/W ADC G-Channel Power Down (SOG Circuit always enable) //(0) 0: ADC Power Down 1: Normal 0 R/W ADC B-Channel Power Down (SOG Circuit always enable) //(0) 0: ADC Power Down 1: Normal Address: E7 ADC_REG_CUR_L Bit Mode Function 7:6 R/W ADC master bias current option: vicm, vocm buffer op bias 00 45u 01 60u 10 75u 11 90u 5:4 R/W ADC master bias voltage option: vicm voltage 00 0.98V 01 1.08V 10 1.20V 11 1.32V Default: 80h
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Default: 69h
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Realtek
3:2 R/W ADC master bias voltage option: vocm voltage 00 1.44V 01 1.56V 10 1.68V 11 1.80V ADC master bias current option: ADC op bias 00 45u 01 60u 10 75u 11 90u ADC_REG_CUR_H
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1:0
R/W
Address: E8 Bit Mode 7:6 R/W 5:4 R/W 3:2 R/W 1 R/W
Default: 15h Function ADC_REG_CLK: Adjust digital clock ( ADC_PIXEL_OUT) and analog clock ( CKOAD) delay ADC_REG_CLK: fine tune GREEN channel phase, hidden.<1:0>, adjust sampling phase in SHA ADC_REG_CLK: adjust non-overlapped time in clock generator ADC_MODE_DUTY: 0: 1F (Using normal pixel rate from APLL) 1: 2F (Using double pixel rate from APLL) 0 R/W ADC_REG_CUR: ADC master bias option, hidden. 0: 1.12387V 1: 1.19873V We have 8 level ADC fine tune phase of RGB, the first is 400ps, and the 2 nd to 7th are each 150ps. Address: E9 ADC_REG_TEST Bit Mode Function 7:5 R/W ADC_REG_TEST //(000) ADC select mux output to ADC_TEST pin in test mode, hidden. 000 Enable clamping buffer 001 Disable clamping buffer 010 test, Voffset connected to SOGIN 011 test, Vicm connected to SOGIN 100 test, Vrb connected to SOGIN 101 test, Vocm connected to SOGIN 110 test, Vrt connected to SOGIN 111 test, Vmid connected to SOGIN 4:3 R/W ADC REG_BND //(10) 00: 75MHz 01: 150MHz 10: 300MHz 11: 500MHz 2 R/W ADC Output (Only when CR[EA]-Bit4=0) 0: Dual output 1: Single output ( Even / Odd selected by CR[EA]-bit7:5 ) 1:0 R/W ADC_REG_OUT //(000) ADC select divider ratio in test mode, hidden. 00 divided by 1 01 divided by 2 10 divided by 3 11 divided by 4 Address: EA ADC_REG_CLK Bit Mode 7 R/W ADC red channel select: 0: even 1: odd 6 R/W ADC green channel select: Default: 10h
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Default: 05h Function
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Realtek
5 R/W
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0: even 1: odd ADC blue channel select: 0: even 1: odd ADC MODE 0: dual channel 1: single channel ADC_REG_CLK_R25: fine tune RED channel phase, hidden.<1:0>, adjust sampling phase in SHA ADC_REG_CLK_B25: fine tune BLUE channel phase, hidden.<1:0>, adjust sampling phase in SHA
4
R/W
3:2 1:0
R/W R/W
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Address: EB ADC Frame Modulation Default: 00h Bit Mode Function 7:6 R/W Power -on-reset Negative Threshold Voltage 00: 1.8V 01: 2.0V 10: 2.2V 11: 2.4V 5 R/W ADC_REG_CLK_R25: fine tune RED channel phase, hidden.<2>, adjust sampling phase in SHA 4 R/W ADC_REG_CLK_G25: fine tune GREEN channel phase, hidden.<2>, adjust sampling phase in SHA 3 R/W ADC_REG_CLK_B25: fine tune BLUE channel phase, hidden.<2>, adjust sampling phase in SHA 2 R/W 0 frame modulation off, disable VS 1 frame modulation on, enable VS 1 R/W 0 disable HS 1 enable HS 0 R/W 0 negative input polarity 1 positive input polarity Address: EC ADC Differential Mode Bit Mode 7 R/W ADC Dual Input Selection 0: Channel 0 1: Channel 1 6 R/W ADC Differential Input Selection 0: Single-ended 1: Differential 5:3 R/W ADC Clamp Voltage Option 2 R/W ADC Red Channel Clamp Selection 0: To ground 1: To mid-scale 1 R/W ADC Green Channel Clamp Selection 0: To ground 1: To mid-scale 0 R/W ADC Blue Channel Clamp Selection 0: To ground 1: To mid-scale Note: 0xEC[7] must be 0. Default: 08h Function
Address: ED HS Schmitt Trigger Control Bit Mode Function 7 R/W HS Power Down (only for Schmitt trigger new mode 0xED[5] =1) 0: Power down 1: Normal
Default: 00h
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Realtek
6 R/W
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Polarity Select 0: Negative HSYNC (high level) 1: Positive HSYNC (low level) Schmitt Trigger Mode 0: Old mode 1: New mode Threshold Voltage Fine Tune (only for Schmitt trigger new mode 0xED[5] =1) 0: 0V 1: -0.1V Positive Threshold Voltage Negative Threshold Voltage
5
R/W
4
R/W
3:2 1:0
R/W R/W
We have 3 mode of the HSYNC Schmitt trigger. 1. Old mode 1: original HSYNC Schmitt trigger. The 0xED [6:5] a 00, The Vt+ = 1.5V, Vt- = 1.0V 2. Old mode 2: The easy HSYNC Schmitt trigger. The 0xED [6:5] a 10 Vt0xED [1:0] Vt+ 01 11 2.0V 1.5V 1.5V 1.0V
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3. New mode: Fully programmable Schmitt trigger. The following table will determine the Schmitt Trigger positive and negative voltage: 0xED [6] = 1 0xED [6] = 0 0xED [3:2] 0xED [1:0] 0xED [3:2] 0xED [1:0] 00: Vt+ = 1.4V 00: Vt- = Vt+ - 1.2V 00: Vt+ = 2.0V 00: Vt- = Vt+ - 1.2V + + + 01: Vt = 1.6V 01: Vt = Vt - 1.0V 01: Vt = 2.2V 01: Vt- = Vt+ - 1.0V + + + 10: Vt = 1.8V 10: Vt = Vt - 0.8V 10: Vt = 2.4V 10: Vt- = Vt+ - 0.8V + + + 11: Vt = 2.0V 11: V t = Vt - 0.6V 11: Vt = 2.6V 11: V t- = Vt+ - 0.6V After we get the threshold voltage by the table, we still can fine tune it: Final Positive Threshold Voltage = Vt+ - 0.1* 0xED[4] Final Negative Threshold Voltage = Vt- - 0.1* 0xED[4]
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Realtek
DDC Special Function Access
RTD2523/2513
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The following DDC special function registers are only valid when EXT# =0. Address: F0 DDC_SET_SLAVE Default: 6E Bit Mode Function 7:1 R/W DDC Slave Address to decode 0 R/W Channel Select 0: from ADC 1: from DVI Address: F1 DDC_SUB_IN Bit Mode Function 7:0 R DDC Sub-Address Received Address: F2 DDC_DATA_IN Bit Mode Function 7:0 R DDC Data Received Address: F3 DDC_DATA_OUT Function Bit Mode 7:0 W DDC Data Output Address: F4 DDC_STATUS Bit Mode Function 7:5 ---Reserved 4 R If DDC_STOP signal occurs, this bit is set to "1" 3 R If DDC_DATA_OUT loaded to serial-out-byte, this bit is set to "1" 2 R If DDC_DATA_IN latched, this bit is set to "1" 1 R If DDC_SUB latched, this bit is set to "1" 0 R If DDC_SLAVE latched, this bit is set to "1" Write to clear status. Address: F5 DDC_IRQ_CTRL Default: 00h Function Bit Mode 7:5 --Reserved 4 R/W 0: Disable the DDC_STOP signal as an interrupt source 1: Enable the DDC_STOP signal as an interrupt source 3 R/W 0: Disable the DDC_DATA_OUT loaded to serial-out-byte as an interrupt source 1: Enable the DDC_DATA_OUT loaded to serial-out-byte as an interrupt source 2 R/W 0: Disable the DDC_DATA_IN latched as an interrupt source 1: Enable the DDC_DATA_IN latched as an interrupt source 1 R/W 0: Disable the DDC_SUB latched as an interrupt source 1: Enable the DDC_SUB latched as an interrupt source 0 R/W 0: Disable the DDC_SLAVE latched as an interrupt source 1: Enable the DDC_SLAVE latched as an interrupt source
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Realtek
DDC Channel
(Refers to the VESA "Display Data Channel Standard" for detailed) Address: FC DDC_ENABLE (DDC Channel Enable Register) Bit Mode Function 7:5 R/W DDC Channel Address Least Significant 3 Bits (The default DDC channel address MSB 4 Bits is "A") 4 R/W DDC Write Status (for external DDC access only) It is cleared after write. 3 R/W DDC SRAM Write Enable (for external DDC access only) 0: Disable 1: Enable 2 R/W DDC Debounce Enable 0: Disable 1: Enable (with crystal/4) 1 R/W DDC Channel RAM Size 0: 128 bytes 1: 256 bytes 0 R/W DDC Channel Enable Bit 0: MCU access Enable 1: DDC channel Enable
RTD2523/2513
Default: 00h
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Address: FD DDC_INDEX (DDC SRAM R/W Index Register) Bit Mode Function 7:0 R/W DDC SRAM Read/Write Index Register [7:0] The DDC channel index register will be auto increased one by one after each read or write cycle. Address: FE DDC_ACCESS_PORT (DDC Channel ACCESS Port) Function Bit Mode 7:0 R/W DDC SRAM Read/Write Port ** The DDC function can still work when Power_Down & Power_Save. ** After reset, the register will be set to default value, but the SRAM will keep original data. Address: FF TMDS Hsync & Vsync Error Correction Function Bit Mode 2 R/W ADC Digital Filter 0: Disable 1: Enable 1:0 R/W TMDS Enhancement 00: orignal output 01: one pixel debouncing 10: one + eight pixels debouncing 11: one+ eight pixels debouncing & masking Default: 00h
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Realtek
Timing Controller
RTD Register Description for Embedded Timing Controller: Address: 95 TCON_ADDR _PORT Bit Mode Function 7:0 R/W Address port for embedded TCON access Address: 96 TCON_DATA _PORT Bit Mode 7:0 R/W Data port for embedded TCON access
RTD2523/2513
Default: 00h
Function
Register Description
Timing Controller Programmable Registers: Address: 00 TC_CTRL1 (Timing Controller control register1) Bit Mode Function 7 R/W Enable Timing Controller Function (Global) 0: Disable 1: Enable 6 R/W TCON [12] / PWM2 Select 0: TCON [12] or crystal output (reference to TCON 0x00[2]) 1: PWM2 5 R/W TCON [n] Toggle Function Reset 0: Not reset 1: reset by DVS 4 R/W TCON [2] Output Function Select (only for serial port access) 0: Original TCON 1: PWM2 3 R/W Inactive Period Data Controlled by internal TCON [13] 0: DEN 1: TCON [13] 2 R/W TCON [12] Set to Crystal Output (only for TCON 0x00[6] = 0 ) 0: Disable 1: Enable 1 R/W TCON [13] Set to Crystal Output (only for TCON 0x04[2] = 0 ) 0: Disable 1: Enable 0 R Power-On latch PLL Test Pin 2 for crystal frequency 0: x 1/2 1: x 1 After switch display timing or clock, 0x00[5] first must be 1 to reset TCON state. Address: 01 TC_CTRL2 (Timing Controller control register2) Bit Mode Function 7 R/W DCLK Slew-Rate Control 0: fast 1: slow 6:4 R/W DCLK Drive Control (ACLKP/ACLKN/BCLKP/BCLKN) 000: Lowest Drive (2mA) ~ 111: Highest Drive (16mA) for TTL 000~111: (C2)*2 + (C1)*1 + (C1)*0.5 + 2.5 mA for RSDS 3 R/W OCLK Slew-Rate Control (pin112) 0: fast 1: slow 2:0 R/W OCLK Drive Current Control (pin112) 000: Lowest Drive (2mA) ~ 111: Highest Drive (16mA) for TTL Address: 02 PURE_TTL_PIN_DRV Default: 0000_011xb
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Default: 00h
Default: 00h
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Realtek
Bit 7 Mode Function R/W Display Data Port Slew-Rate Control 0: fast 1: slow R/W Display Data Port Drive Current Control 000: Lowest Drive (2mA) ~ 111: Highest Drive (16mA) R/W TCON Slew-Rate Control 0: fast 1: slow R/W TCON Drive Current Control 000: Lowest Drive (2mA) ~ 111: Highest Drive (16mA)
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6:4 3
2:0
Address: 03 RSDS Performance Fine Tune Bit Mode Function 7:6 R/W Display Port Configuration: 00: TTL 01: HZ 10: LVDS 11: RSDS 5 R/W RSDS Green / Clock Pair Swap 4:2 R/W Display Data Port Drive Current Control (for LVDS pin) 000~111: (C2)*4 + (C1)*4 + (C0)*2 mA for TTL (C2~C0 is bit 6~4) 1 R/W RSDS High/Low Bit Swap (data) 0 R/W RSDS Differential pair PN swap (data)
Default: 40h
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//**Example: AU 17" RSDS panel pin order: B0B1B2G0G1G2CLKR0R1R2 QDI 17" RSDS panel pin order: B2B1B0G2G1G0CLKR2R1R0 CMO 17" RSDS panel pin order: B2B1B0CLKG2G1G0R2R1R0 RTD even/odd swap,red/blue swap,8 bit MSB/LSB swap,6 bit MSB/LSB swap, RSDS high/low bit swap, RSDS P/N swap, green/clk swap , -if 6Bit MSB/LSB swap,then G0G1G2CLK -> G2G1G0CLK -if green/clock swap, then G0G1G2CLK -> CLKG0G1G2 -if 6Bit MSB/LSB swap first, then green/clk swap G0G1G2CLK -> G2G1G0CLK-> CLKG2G1G0 **// Address: 04 DDC _PARA_VIDEO8_TCON_PWM_SHARING Function Bit Mode 7 R/W TMDS_DDC Enable 0: Disable 1: Enable 6 R/W ADC_DDC Enable 0: Disable 1: Enable 5 --Reserved 4 R/W TTL Display B port Blue [1:0] Location (only for TTL 8bit mode) 0: From pin 52, 53 (must be serial port) 1: From pin 46, 47 (TCON 0x04[6] = 0) 3 R/W VIDEO-8 port Input / Output Enable 0: Output 1: Input Default: F8h
83
Realtek
2 R/W
RTD2523/2513
TCON [13] / PWM2 Select 0: TCON [13] or crystal output (reference to TCON 0x00[1]) 1: PWM2 TCON [7] / PWM1 Select (only for TCON 0x04[7] = 0) 0: TCON [7] 1: PWM1 TCON [1] / PWM1 Select Bit 0 (only for TCON 0x04[6] = 0 && TCON 0x04[4] = 0) 0: TCON [1] 1: PWM1
1
R/W
0
R/W
Address: 05 RSDS_PIN_DRV (pin 59~108) Default: 00h Function Bit Mode 7 R/W Display Data Port Slew-Rate Control (for LVDS pin) 0: fast 1: slow 6:4 R/W Display Data Port Drive Current Control (for LVDS pin) 000~111: (C2)*4 + (C1)*4 + (C0)*2 mA for TTL (C2~C0 is bit 6~4) 000~111: (C2)*2 + (C1)*1 + (C1)*0.5 + 2.5 mA for RSDS & LVDS (C2~C0 is bit6~4) 3 R/W TCON Slew-Rate Control (for LVDS pin) 0: fast 1: slow 2:0 R/W TCON Drive Current Control (for LVDS pin) 000~111: (C2)*4 + (C1)*4 + (C0)*2 mA for TTL (C2~C0 is bit 2~0) Address: 06~07 Reserved for future Address: 08 Bit Mode 7:0 W Address: 09 Bit Mode 7 6:4 W 3 2:0 W Address: 0A Bit Mode 7:0 W TCON [0]_VS_LSB (TCON [0] Vertical Start LSB Register) Function Line number [7:0] at which TCON control generation begins TCON [0]_VS_MSB (TCON [0] Vertical Start/End MSB Register) Function Reserved Line number [10:8] at which TCON control generation ends Reserved Line number [10:8] at which TCON control generation begins TCON [0]_VE_LSB (TCON [0] Vertical End LSB Register) Function Line number [7:0] at which TCON control generation ends
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Address: 0B TCON [0]_HS_LSB (TCON [0] Horizontal Start LSB Register) Bit Mode Function 7:0 W Pixel count [7:0] at which TCON goes active Address: 0C TCON [0]_HS_MSB (TCON [0] Horizontal Start/End MSB Register) Bit Mode Function 7 Reserved 6:4 W Pixel count [10:8] at which TCON goes inactive 3 Reserved 2:0 W Pixel count [10:8] at which TCON goes active Notes: To be triggered on rising edge of the DCLK Address: 0D TCON [0]_HE_LSB (TCON [0] Horizontal End LSB Register) Bit Mode Function 7:0 W Pixel count [7:0] at which TCON goes inactive Notes: If the register number is large than display format, the horizontal component is always on.
84
Realtek
RTD2523/2513
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Address: 0E TCON [0]_CTRL (TCON [0] Control Register) Default: 00h Bit Mode Function 7 R/W TCON [n] Enable (Local) 0: Disable (TCON [n] output clamp to `0') 1: Enable 6 R/W Polarity Control 0: Normal output 1: Inverted output 5 ---Reserved 4 ---Reserved 3 R/W Toggle Circuit Enable/Disable 0: Normal TCON output 1: Toggle Circuit enable 2:0 R/W TCON [13:10] & TCON [7:4] (TCON Combination Select) /*TCON [13] has inactive data controller function. TCON [13]~[10] has dot masking function TCON [7] has flicking reduce function. */ 000: Normal TCON output 001: Select TCON [n] "AND" with TCON [n-1] 010: Select TCON [n] "OR" with TCON [n-1] 011: Select TCON [n] "XOR" with TCON [n-1] 100: Select TCON [n-1] rising edge as toggle trigger signal (when toggle enable) 101: Select TCON [n-1] rising edge as toggle trigger signal, then "AND" (when toggle enable) 110: Select TCON [n-1] rising edge as toggle trigger signal, then "OR" (when toggle enable) 111: Select TCON [n] and TCON [n-1] on alternating frames. -------------------------------------------------------------------------------------------------------------------TCON [9:8] (TCON Combination Select) 000: Normal TCON output 001: Select TCON [n] "AND" with TCON [n-1] 010: Select TCON [n] "OR" with TCON [n-1] 011: Select TCON [n] "XOR" with TCON [n-1] 100: Select TCON [n-1] rising edge as toggle trigger signal (when toggle enable) 101: Select TCON [n-1] rising edge as toggle trigger signal, then "AND" (when toggle enable) 110: Select TCON [n-1] rising edge as toggle trigger signal, then "OR" (when toggle enable) 111: Select TCON [n] and TCON [n-1] reference ODD signal as alternating frames. -------------------------------------------------------------------------------------------------------------------TCON [3] (TCON Combination Select) 000: Normal TCON output 001: Select TCON [3] "AND" with TCON [2] 010: Select TCON [3] "OR" with TCON [2] 011: Select TCON [3] "XOR" with TCON [2] 100: Select TCON [2] rising edge as toggle trigger signal (when toggle enable) 101: Select TCON [2] rising edge as toggle trigger signal, then "AND" (when toggle enable) 110: Select TCON [2] rising edge as toggle trigger signal, then "OR" (when toggle enable) 111: Select reset(ODD=0) or set(ODD=1) TCON [3] by DVS, when toggle function enable -------------------------------------------------------------------------------------------------------------------TCON [2] (Clock Toggle Function)//toggle function is inactive 00x: Normal TCON output 010: Select DCLK/2 when TCON [2] is "0" 011: Select DCLK/2 when TCON [2] is "1" 100: Select DCLK/4 when TCON [2] is "0" 101: Select DCLK/4 when TCON [2] is "1" 110: Select DCLK/8 when TCON [2] is "0" 111: Select DCLK/8 when TCON [2] is "1" -------------------------------------------------------------------------------------------------------------------TCON [1] xx0: Normal TCON output xx1: Reverse-Control Signal output
85
Realtek
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-------------------------------------------------------------------------------------------------------------------TCON [0] 00x: Normal TCON output 010: EVEN "REV" 18/24-bit function ("REV0" on TCON [0]) ODD "REV" 18/24-bit function ("REV1" on TCON [1]) 011: ALL "REV" 36/48-bit function ("REV" on TCON [0], can also on TCON [1]) 100: EVEN data Output Inversion Controlled by TCON [0] is "0" ODD data Output Inversion Controlled by TCON [1] is "0" 101: EVEN data Output Inversion Controlled by TCON [0] is "1" ODD data Output Inversion Controlled by TCON [1] is "1"
Address: 5F/67/6F/77 TC_DOT_MASKING_CTRL Bit Mode 7:3 R/W Reserved 2 R/W Red Dot Masking Enable 0: Disable 1: Enable 1 R/W Green Dot Masking Enable 0: Disable 1: Enable 0 R/W Blue Dot Masking Enable 0: Disable 1: Enable
Default: 00h Function
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86
Realtek
TCON [0] ~ TCON [13] Control Registers Address Map Address Data(# bits) 0A,09,08 TCON [0]_VS_REG (11) 0D,0C,0B TCON [0]_HS_REG (11) 0E TCON [0]_CTRL_REG 0F Reserved 12,11,10 15,14,13 16 17 1A,19,18 1D,1C,1B 1E 1F 22,21,20 25,24,23 26 27 2A,29,28 2D,2C,2B 2E 2F
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RTD2523/2513
Default
00
TCON [1]_VS_REG (11) TCON [1]_HS_REG (11) TCON [1]_CTRL_REG Reserved TCON [2]_VS_REG (11) TCON [2]_HS_REG (11) TCON [2]_CTRL_REG Reserved TCON [3]_VS_REG (11) TCON [3]_HS_REG (11) TCON [3]_CTRL_REG Reserved TCON [4]_VS_REG (11) TCON [4]_HS_REG (11) TCON [4]_CTRL_REG Reserved TCON [5]_VS_REG (11) TCON [5]_HS_REG (11) TCON [5]_CTRL_REG Reserved TCON [6]_VS_REG (11) TCON [6]_HS_REG (11) TCON [6]_CTRL_REG Reserved TCON [7]_VS_REG (11) TCON [7]_HS_REG (11) TCON [7]_CTRL_REG Reserved TCON [8]_VS_REG (11) TCON [8]_HS_REG (11) TCON [8]_CTRL_REG Reserved TCON [9]_VS_REG (11) TCON [9]_HS_REG (11) TCON [9]_CTRL_REG Reserved TCON [10]_VS_REG (11)
00
00
00
00
32,31,30 35,34,33 36 37 3A,39,38 3D,3C,3B 3E 3F 42,41,40 45,44,43 46 47 4A,49,48 4D,4C,4B 4E 4F 52,51,50 55,54,53 56 57 5A,59,58
00
00
00
00
00
87
Realtek
5D,5C,5B 5E 5F 62,61,60 65,64,63 66 67 6A,69,68 6D,6C,6B 6E 6F 72,71,70 75,74,73 76 77 TCON [10]_HS_REG (11) TCON [10]_CTRL_REG TCON [10]_CTRL_REG TCON [11]_VS_REG (11) TCON [11]_HS_REG (11) TCON [11]_CTRL_REG TCON [11]_CTRL_REG TCON [12]_VS_REG (11) TCON [12]_HS_REG (11) TCON [12]_CTRL_REG TCON [12]_CTRL_REG TCON [13]_VS_REG (11) TCON [13]_HS_REG (11) TCON [13]_CTRL_REG TCON [13]_CTRL_REG 00
RTD2523/2513
00 00
00 00
00 00
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88
Realtek
Embedded OSD
Register Access and address
Addressing and Accessing Register
RTD2523/2513
BIT 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 High Byte A7 A6 A5 A4 A3 A2 A1 A0 Low Byte Figure 16. Addressing and Accessing Registers Date BIT D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 Byte 2 Figure 2. Data Registers All kind of registers can be controlled and accessed by these 2 bytes, and each address contains 3-byte data, details are described as follows: Write mode: [A15:A14] select which byte to write -00: Byte 0 -01:Byte 1 -10: Byte 2 -11: All *All data are sorted by these three Bytes (Byte0~Byte2) [A13] Auto Load (After write 6 byte to buffer, load data wait VSync porch) [A12] Address indicator -0: Window and frame control and hardware cursor registers. -1: Font Select and font map SRAM [A11:A0] Address mapping - Font Select and font map SRAM address: 000~EFF 3.75k*3byte -Frame control register address: 000~0xx (Latch) -Window control register address: 100~1xx (Latch) -Hardware cursor(36x36 pixel) RAM: 200~26b (SRAM) * Selection of SRAM address or Latch address selection is determined by A12! Example. Bit [15:14]=00 -All data followed are written to byte0 and address increases.
Byte0aByte0aByte0... (Address will auto increase)
ADDRESS
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Bit [15:14] =01 -All data followed are written to byte1 and address increases.
Byte1aByte1aByte1... (Address will auto increase)
Bit [15:14] =11 - Address will be increased after each 3-byte data written.
Byte0aByte1aByte2aByte0aByte1aByte2... (Address will auto increase)
89
Realtek
Window control registers
l l l l l
RTD2523/2513
Windows all support shadow/border/3D button Window0, 5, 6, 7 support gradient functions. Window 4, 5, 6, 7 start/end resolution are 1line(pixel), Window 0, 1, 2, 3 start/end resolution are 4line(pixel), All window start and end position include the special effect (border/shadow/3D button) been assigned Font comes after windows by 10 pixels, so you should compensate 10 pixels on windows to meet font position
Window 0 Shadow/Border/Gradient Address: 100h Byte 0 Bit 7:6 5:3 2:0
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Mode Function -Reserved W Window 0 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel W Window 0 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness
Byte 1 Bit 7:4 3:0 Byte 2 Bit 7
Mode Function W Window 0 shadow color index in 16-color LUT For 3D window, it is the left-top/bottom border color W Window 0 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color Mode W R Gradient Polarity 0: Decrease 1: Increase W G Gradient Polarity 0: Decrease 1: Increase W B Gradient Polarity 0: Decrease 1: Increase W Gradient level 00: 1 step per level 01: Repeat 2 step per level 10: Repeat 3 step per level 11: Repeat 4 step per level 90 Function
6
5
4:3
Realtek
2 1 0 W W W Enable Red Color Gradient Enable Green Color Gradient Enable Blue Color Gradient
RTD2523/2513
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91
Realtek
Window 0 start position Address: 101h Byte 0 Bit Mode Function 7:2 W Window 0 horizontal start [5:0] 1:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 0 vertical start [2:0] line 4:0 W Window 0 horizontal start [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 0 vertical start [10:3] line Start position must be increments of four.
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Window 0 end position Address: 102h Byte 0 Bit Mode Function 7:2 W Window 0 horizontal end [5:0] 1:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 0 vertical end [2:0] line 4:0 W Window 0 horizontal end [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 0 vertical end [10:3] line l End position must be increments of four. Window 0 control Address: 103h Byte 0 Bit 7:0 Byte 1 Bit 7 6:4
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Mode -Reserved Mode -Reserved W 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient
Function
Function
92
Realtek
010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient Window 0 color index in 16-color LUT
RTD2523/2513
3:0 Byte 2 Bit 7 6
W
default: 00h Mode W Reserved W Gradient function 0: Disable 1: Enable W Gradient direction 0: Horizontal 1: Vertical W Shadow/Border/3D button 0: Disable 1: Enable W Window 0 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border W Window 0 Enable 0: Disable 1: Enable Function
5
4
3:1
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0
Window 1 Shadow/Border/Gradient Address: 104h Byte 0 Bit 7:6 5:3 2:0
Mode Function W Reserved W Window 1 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel W Window 1 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness
Byte 1 Bit 7:4 3:0
Mode Function W Window 1 shadow color index in 16-color LUT For 3D window, it is the left-top/bottom border color W Window 1 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color
93
Realtek
Byte 2 Bit 7:0 Mode W Reserved Function
RTD2523/2513
Window 1 start position Address: 105h Byte 0 Bit Mode Function 7:2 W Window 1 horizontal start [5:0] 3:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 1 vertical start [2:0] line 4:0 W Window 1 horizontal start [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 1 vertical start [10:3] line Start position must be increments of four.
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Window 1 end position Address: 106h Byte 0 Bit Mode Function 7:2 W Window 1 horizontal end [5:0] 2:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 1 vertical end [2:0] line 4:0 W Window 1 horizontal end [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 1 vertical end [10:3] line End position must be increments of four.
94
Realtek
Window 1 control Address: 107h Byte 0 Bit 7:0 Byte 1 Bit 7:4 3:0 Byte 2 Bit 7:5 4
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Mode -Reserved
Function
Mode Function -Reserved W Window 1 color index in 16-color LUT default: 00h Mode W Reserved W Shadow/Border/3D button 0: Disable 1: Enable W Window 1 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border W Window 1 Enable 0: Disable 1: Enable
Function
3:1
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0
Window 2 Shadow/Border/Gradient Address: 108h Byte 0 Bit 7:6 5:3 2:0
Mode Function W Reserved W Window 2 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel W Window 2 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness
Byte 1 Bit 7:4 3:0
Mode Function W Window 2 shadow color index in 16-color LUT For 3D window, it is the left-top/bottom border color W Window 2 border color index in 16-color LUT 95
Realtek
For 3D window, it is the right-bottom/top border color Byte 2 Bit 7:0 Mode W Reserved Function
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Window 2 start position Address: 109h Byte 0 Bit Mode Function 7:2 W Window 2 horizontal start [5:0] 1:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 2 vertical start [2:0] line 4:0 W Window 2 horizontal start [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 2 vertical start [10:3] line Start position must be increments of four.
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Window 2 end position Address: 10Ah Byte 0 Bit Mode Function 7:2 W Window 2 horizontal end [5:0] 1:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 2 vertical end [2:0] line 4:0 W Window 2 horizontal end [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 2 vertical end [10:3] line End position must be increments of four.
Window 2 control Address: 10Bh Byte 0 Bit 7:0 Byte 1 Bit
Mode -Reserved Mode 96
Function
Function
Realtek
7:4 3:0 Byte 2 Bit 7:5 4 -W Reserved Window 2 color index in 16-color LUT
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default: 00h Mode W Reserved W Shadow/Border/3D button 0: Disable 1: Enable W Window 2 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border W Window 2 Enable 0: Disable 1: Enable Function
3:1
0
Window 3 Shadow/Border/Gradient Address: 10Ch
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Byte 0 Bit 7:6 5:3 2:0
Mode Function W Reserved W Window 3 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel W Window 3 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness
Byte 1 Bit 7:4 3:0 Byte 2 Bit 7:0
Mode Function W Window 3 shadow color index in 16-color LUT For 3D window, it is the left-top/bottom border color W Window 3 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color Mode W Reserved Function
Window 3 start position Address: 10Dh Byte 0 Bit
Mode 97
Function
Realtek
7:2 W Window 3 horizontal start [5:0] 1:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 3 vertical start [2:0] line 4:0 W Window 3 horizontal start [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 3 vertical start [10:3] line Start position must be increments of four.
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Window 3 end position Address: 10Eh Byte 0 Bit Mode Function 7:2 W Window 3 horizontal end [5:0] 1:0 -Reserved Byte 1 Bit Mode Function 7:5 W Window 3 vertical end [2:0] line 4:0 W Window 3 horizontal end [10:6] pixel Byte 2 Bit Mode Function 7:0 W Window 3 vertical end [10:3] line End position must be increments of four.
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Window 3 control Address: 10Fh Byte 0 Bit Mode Function 7:0 -Reserved Byte 1 Bit Mode Function 7:4 -Reserved 3:0 W Window 3 color index in 16-color LUT Byte 2 Bit Mode Function 7:5 W Reserved 4 W Shadow/Border/3D button 0: Disable 1: Enable 3:1 W Window 3 Type 000: Shadow Type 1 001: Shadow Type 2 98
default: 00h
Realtek
010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border Window 3 Enable 0: Disable 1: Enable
RTD2523/2513
0
W
Window 4 Shadow/Border/Gradient Address: 110h Byte 0 Bit 7:6 5:3 2:0
Mode Function W Reserved W Window 4 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel W Window 4 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness Mode Function W Window 4 shadow color index in 16-color LUT For 3D window, it is the left-top/ bottom border color W Window 4 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color Mode W Reserved Function
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Byte 1 Bit 7:4 3:0 Byte 2 Bit 7:0
Window 4 start position Address: 111h Byte 0 Bit 7:2 2:0
Mode Function W Window 4 horizontal start [5:0] -Reserved
Byte 1 Bit 7:5 4:0
Mode Function W Window 4 vertical start [2:0] line W Window 4 horizontal start [10:6] pixel
99
Realtek
Byte 2 Bit 7:0 Mode Function W Window 4 vertical start [10:3] line
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Window 4 end position Address: 112h Byte 0 Bit 7:2 1:0 Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0
Mode W Window 4 horizontal end [5:0] -Reserved
Function
Mode Function W Window 4 vertical end [2:0] line W Window 4 horizontal end [10:6] pixel Mode Function W Window 4 vertical end [10:3] line
Window 4 control Address: 113h
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Byte 0 Bit 7:0 Byte 1 Bit 7:4 3:0 Byte 2 Bit 7:5 4
Mode -Reserved
Function
Mode Function -Reserved W Window 4 color index in 16-color LUT default: 00h Mode W Reserved W Shadow/Border/3D button 0: Disable 1: Enable W Window 4 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border W Window 4 Enable Function
3:1
0
100
Realtek
0: Disable 1: Enable
RTD2523/2513
Window 5 Shadow/Border/Gradient Address: 114h Byte 0 Bit 7:6 5:3 2:0
Mode Function W Reserved W Window 5 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel W Window 5 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness Mode Function W Window 5 shadow color index in 16-color LUT For 3D window, it is the left-top/bottom border color W Window 5 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color Mode W R Gradient Polarity 0: Decrease 1: Increase W G Gradient Polarity 0: Decrease 1: Increase W B Gradient Polarity 0: Decrease 1: Increase W Gradient level 00: 1 step per level 01: Repeat 2 step per level 10: Repeat 3 step per level 11: Repeat 4 step per level W Enable Red Color Gradient W Enable Green Color Gradient W Enable Blue Color Gradient Function
Byte 1 Bit 7:4 3:0 Byte 2 Bit 7
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6
5
4:3
2 1 0
Window 5 start position Address: 115h Byte 0 Bit
Mode 101
Function
Realtek
7:2 1:0 Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0 W -Window 5 horizontal start [5:0] Reserved
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Mode Function W Window 5 vertical start [2:0] line W Window 5 horizontal start [10:6] pixel Mode Function W Window 5 vertical start [10:3] line
Window 5 end position Address: 116h Byte 0 Bit 7:2 1:0 Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0
Mode W Window 5 horizontal end [5:0] -Reserved
Function
Mode Function W Window 5 vertical end [2:0] line W Window 5 horizontal end [10:6] pixel Mode Function W Window 5 vertical end [10:3] line
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Window 5 control Address: 117h Byte 0 Bit 7:0 Byte 1 Bit 7 6:4
Mode -Reserved
Function
3:0
Mode Function -Reserved W 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient W Window 5 color index in 16-color LUT
102
Realtek
Byte 2 Bit 7 6 Mode W Reserved W Gradient function 0: Disable 1: Enable W Gradient direction 0: Horizontal 1: Vertical W Shadow/Border/3D button 0: Disable 1: Enable W Window 5 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border W Window 5 Enable 0: Disable 1: Enable Function
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default: 00h
5
4
3:1
0
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Window 6 Shadow/Border/Gradient Address: 118h Byte 0 Bit 7:6 5:3
Mode Function W Reserved W Window 6 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 W Window 6 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness PS: This is for non-rotary, rotate 270, rotate 90 and 180. Byte 1 Bit Mode Function 7:4 W Window 6 shadow color index in 16-color LUT For 3D window, it is the left-top/ bottom border color 3:0 W Window 6 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color Byte 2 Bit Mode Function 7 W R Gradient Polarity 0: Decrease 1: Increase 103
Realtek
6 W 1: Increase G Gradient Polarity 0: Decrease 1: Increase B Gradient Polarity 0: Decrease 1: Increase Gradient level 00: 1 step per level 01: Repeat 2 step per level 10: Repeat 3 step per level 11: Repeat 4 step per level Enable Red Color Gradient Enable Green Color Gradient Enable Blue Color Gradient
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5
W
4:3
W
2 1 0
W W W
Window 6 start position Address: 119h Byte 0 Bit 7:2 1:0 Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0
Mode Function W Window 6 horizontal start [5:0] -Reserved Mode Function W Window 6 vertical start [2:0] line W Window 6 horizontal start [10:6] pixel Mode Function W Window 6 vertical start [10:3] line
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Window 6 end position Address: 11Ah Byte 0 Bit 7:2 1:0 Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0
Mode W Window 6 horizontal end [5:0] -Reserved
Function
Mode Function W Window 6 vertical end [2:0] line W Window 6 horizontal end [10:6] pixel Mode Function W Window 6 vertical end [10:3] line 104
Realtek
Window 6 control Address: 11Bh Byte 0 Bit 7:0 Byte 1 Bit 7 6:4
RTD2523/2513
Mode -Reserved
Function
3:0 Byte 2 Bit 7 6
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Mode Function -Reserved W 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient W Window 6 color index in 16-color LUT default: 00h Mode W Reserved W Gradient function 0: Disable 1: Enable W Gradient direction 0: Horizontal 1: Vertical W Shadow/Border/3D button 0: Disable 1: Enable W Window 6 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border W Window 6 Enable 0: Disable 1: Enable Function
5
4
3:1
0
105
Realtek
Window 7 Shadow/Border/Gradient Address: 11Ch Byte 0 Bit 7:6 5:3
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Mode Function W Reserved W Window 7 shadow/border width or 3D button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 W Window 7 shadow/border height in line unit 000~111: 1 ~ 8 line It must be the same as bit[5:3] for 3D button thickness PS: This is for non-rotary, rotate 270, rotate 90 and 180. Byte 1 Bit Mode Function 7:4 W Window 7 shadow color index in 16-color LUT For 3D window, it is the left-top/bottom border color 3:0 W Window 7 border color index in 16-color LUT For 3D window, it is the right-bottom/top border color Byte 2 Bit Mode Function 7 W R Gradient Polarity 0: Decrease 1: Increase 6 W G Gradient Polarity 0: Decrease 1: Increase 5 W B Gradient Polarity 0: Decrease 1: Increase 4:3 W Gradient level 00: 1 step per level 01: Repeat 2 step per level 10: Repeat 3 step per level 11: Repeat 4 step per level 2 W Enable Red Color Gradient 1 W Enable Green Color Gradient 0 W Enable Blue Color Gradient
Window 7 start position Address: 11Dh Byte 0 Bit 7:2 1:0
Mode Function W Window 7 horizontal start [5:0] -Reserved
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Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0 Mode Function W Window 7 vertical start [2:0] line W Window 7 horizontal start [10:6] pixel Mode Function W Window 7 vertical start [10:3] line
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Window 7 end position Address: 11Eh Byte 0 Bit 7:2 1:0 Byte 1 Bit 7:5 4:0 Byte 2 Bit 7:0
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Mode W Window 7 horizontal end [5:0] -Reserved
Function
Mode Function W Window 7 vertical end [2:0] line W Window 7 horizontal end [10:6] pixel Mode Function W Window 7 vertical end [10:3] line
Window 7 control Address: 11Fh Byte 0 Bit 7:0 Byte 1 Bit 7 6:4
Mode -Reserved
Function
3:0 Byte 2 00h Bit 7 6
Mode Function -Reserved W 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient W Window 7 color index in 16-color LUT default: Mode W Reserved W Gradient function 107 Function
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5 W 0: Disable 1: Enable Gradient direction 0: Horizontal 1: Vertical Shadow/Border/3D button 0: Disable 1: Enable Window 7 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border Window 7 Enable 0: Disable 1: Enable
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4
W
3:1
W
0
W
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108
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3D Button Type 1
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3D Button Type 2
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width
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height Type 1 Type 2 Type 3 Type 4
Shadow in all direction
start
OSD appear range
transparent
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end
Window mask fade/in out function
110
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Frame control registers
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Address: 000h Byte 0 Bit Mode Function 7:0 W Vertical Delay [8:1] The bits define the vertical starting address. Total 512 step unit: 4 line Vertical delay minimum should set 1 Byte 1 Bit Mode Function 7:0 W Horizontal Delay [9:2] The bits define the horizontal starting address. Total 1024 step unit:4 pixels Horizontal delay minimum should set 2 Byte 2 Bit Mode Function 7:6 W Horizontal Delay bit [1:0] 5 W Vertical Delay [0] 4 W Global Blinking Enable 0: Disable 1: Enable Note: In order to make blinking function work, add redundant OSD row command to next DVS occurrence. 3:2 W Display zone, for smaller character width 00: middle 01: left 10: right 11: reserved 1 W Rotation 0: Normal (data latch 24 bit per 24 bit) 1: Rotation (data latch 18 bit per 24 bit) 0 W OSD enable 0: OSD circuit is inactivated 1: OSD circuit is activated When OSD is disabled, Double Width (address 0x002 Byte1[1]) must be disabled to save power.
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PWM Duty Width Address: 001h Byte 0 Bit Mode Function 7:0 W PWM_0 8bits decides the output duty width and waveform of PWM at PWM channel Byte 1 Bit Mode Function 7:0 W PWM_1 8bits decides the output duty width and waveform of PWM at PWM channel Byte 2 Bit Mode Function 7:0 W PWM_2 8bits decides the output duty width and waveform of PWM at PWM channel PWM _Control Address: 002h Byte 0 default: xxxx_xxx0b Bit Mode Function 7 -Reserved 6 W Enable Window 7 Mask OSD-Appear-Range Control for Fade In/Out 5 W Window 7 Mask 0: Mask area appears 1: Mask area transparent 4 W OSD vertical start input signal source select 0: Select DVS as OSD VSYNC input 1: Select ENA as OSD VSYNC input 3:2 W 00:PWM_CLK/1 01:PWM_CLK/2 10:PWM_CLK/4 11:PWM_CLK/8 1 W PWM Clock Source From 0:DCLK , 1:Crystal Clock 0 W Enable PWM output Byte 1 Bit Mode Function 7:4 W Char shadow/border color 3 W Blending Enable 2 W Blending type 0: All blending (including window, character, character background, cursor) 1: Only window and character background blending 1 W Double width enable (For all OSD including windows and characters) 0: Normal 1: Double 0 W Double Height enable (For all OSD including windows and characters) 0: Normal 1: Double
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Byte 2 Bit 7:6 Mode W Font downloaded swap control 0x: No swap 10: CCW 11: CW -Reserved 7 A A E 6 B E A 5 C B F 4 D F B Function
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5:0 Bit Firmware CW CCW
3 E C G
2 F G C
1 G D H
0 H H D
23~12 bit(High) 11~0 bit(Low)
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Figure 3 Non-rotated memory alignments 6
Figure 4 Rotated memory alignments
Base address offset 113
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Address: 003h Byte 0 Bit Mode 7:0 W Byte 1 Bit Mode 7:4 W 3:0 W Byte 2 Bit Mode 7:0 W Function Font Select Base Address[7:0] Function Font Select Base Address[11:8] Font Base Address[3:0] Function Font Base Address[11:4]
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OSD SRAM (Map and font registers)
R0 R1 R2 C01 C02 B03 C04 Rn End C11 C12 C13 ... ... Cn1 Cn2 ... 1-bit font start ... 2-bit font start ... ... ... ... ... ... ....
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...
... ... 4-bit font start
...
11.25k bytes SRAM
1. Row Command
R0
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R1
R2
R3
R... .
Rn
End
Row Command R0~Rn represent the start of new row. Each command contains 3 bytes data which define the length of a row and other attributes. OSD End Command represent the end of OSD. R0 is set in address 0 of SRAM.
2. Character/Blank Command (Font Select) Character Command is used to select which character font is show. Each command contains three bytes which specify its attribute and 1,2 or 4bit per pixel. Blank Command represents blank pixel to separate the preceding character and following character. Use two or more Blank Command if the character distance exceeds 255 pixel.
The Font Select Base Address in Frame Control Register represents the address of the first character in Row 0, that is, C01 in the above figure. The following character/blank is write in the next address. C11 represents the first character in Row1, C12 represents the second character in Row1, and so on. The address of the first character Cn1 in Row n = Font Select Base Address + Row 0 font base length + Row 1 font base length + ... +Row n-1 font base length.
3. Font User fonts are stored as bit map data. For normal font, one font has 12x18 pixel, and for rotation font, one has 18x12 pixel. One pixel use 1, 2 or 4 bits. For 12x18 font, One 1-bit font requires 9 * 24bit SRAM One 2-bit font requires 18 * 24bit SRAM One 4-bit font requires 36 * 24bit SRAM 115
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For 18x12 font, One 1-bit font requires 12 * 24bit SRAM One 2-bit font requires 24 * 24bit SRAM One 4-bit font requires 48 * 24bit SRAM
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Font Base Address in Frame Control Register point to the start of 1-bit font. For normal (12x18) font: 1-bit Font, if CS = 128, Real Address of Font = Font Base Address + 9 * 128 2-bit Font, if CS = 128, Real Address of Font = Font Base Address + 18 * 128 4-bit Font, if CS = 128, Real Address of Font = Font Base Address + 36 * 128 For rotational (18x12) font: 1-bit Font, if CS = 128, Real Address of Font = Font Base Address + 12 * 128 2-bit Font, if CS = 128, Real Address of Font = Font Base Address + 24 * 128 4-bit Font, if CS = 128, Real Address of Font = Font Base Address + 48 * 128 where CS is Character Selector in Character Command. Note that Row Command, Font Select and Font share the same OSD SRAM. When we download the font, we have to set the Frame control 002h byte1 [1:0] to set the method of hardware bit swap. If the OSD is Counter-Clock-Wise rotated, we have to set to 0x01 (the 8 bits of every byte of font SRAM downloaded by firmware will be in a sequence of "7 5 3 1 6 4 2 0" (from MSB to LSB) and should be rearranged to "7 6 5 4 3 2 1 0" by hardware). If it is Clock-Wise rotated, we have to set to 0x10 (the 8 bits of every byte of font SRAM downloaded by firmware will be in a sequence of "6 4 2 0 7 5 3 1" (from MSB to LSB) and should be rearranged to "7 6 5 4 3 2 1 0" by hardware). After we finish the downloading or if we don't have to rotate the OSD, we have to set it to 0x00. Row Command Byte 0 Bit 7
6:5 4:2
1
0
Mode Function W 1: Row Start Command 0: OSD End Command Each row must start with row-command, last word of OSD map must be end-command W Reserved W Character border/shadow 000: None 001: Border 100: Shadow (left-top) 101: Shadow (left-bottom) 110: Shadow (right-top) 111: Shadow (right-bottom) W Double character width 0: x1 1: x2 W Double character height 0: x1 1: x2 116
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Byte 1 Bit 7:3 2:0 Mode Function W Row height (1~32) W Column space 0~7 pixel column space When Char is doubled, so is column space.
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Notice: When character height/width is doubled, the row height/column space definition also twice. If the row height is larger than character height, the effect is just like space between rows. If it is smaller than character height, it will drop last several bottom line of character. When using 1/2/4LUT font, column space and font smaller than row height, the color of column space and row space is the same as font background color, only 4 bit true color font mode, the color is transparent 12
25
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A
Row space color
column space color
1/2/4LUT bg color the same as Character background ,4 true color mode, bg color is transparent
Byte 2 Bit 7:0
Mode W Row length
Function unit: font base
Blank Command Byte 0 Bit Mode 7 W 0 6 W Blinking effect 0: Disable 1: Enable 5:0 W Reserved 117
Function
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Byte 1 Bit Mode Function 7:0 W Blank pixel length At least 3 pixels, and can't exceed 255 pixels. Byte 2 Bit Mode Function 7:5 W Reserved 4 W Reserved 3:0 W Blank color - select one of 16-color LUT (0 is special for transparent)
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Character Command (For 1-bit RAM font) Byte 0 Bit Mode Function 7 W 1 6 W Character Blinking effect 0: Disable 1: Enable 5:4 W 00 (Font type 00: 1-bit RAM Font 01: 4-bit RAM Font 1x: 2-bit RAM Font) 3:0 W Character width (only for 1-pixel font, doubled when specifying double-width in Row/Blank command register) For 12x18 font: 0100: 4-pixel 0101: 5-pixel 0110: 6-pixel 0111: 7-pixel 1000: 8-pixel 1001: 9-pixel 1010: 10-pixel 1011:11-pixel 1100: 12-pixel For 18x12 Font (rotated) 0000: 4-pixel 0001: 5-pixel 0010: 6-pixel 0011: 7-pixel 0100: 8-pixel 0101: 9-pixel 0110: 10-pixel 0111: 11-pixel 1000: 12-pixel 1001:13-pixel 1010:14-pixel 1011:15-pixel 1100: 16-pixel 1101:17-pixel 1110:18-pixel When using border/shadow/ effect, the width of the 1-bit font should at least 6 pixel.
Byte 1 Bit 7:0 Byte 2 Bit 7:4 3:0
Mode W Character Select [7:0]
Function
Mode Function W Foreground color Select one of 16-color from color LUT W Background color 118
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Select one of 16-color from color LUT (0 is special for transparent)
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Character command (For 2-bit RAM Font) Byte 0 Bit Mode Function 7 W 1 6 W Character Blinking effect 0: Disable 1: Enable 5 W 1 4 W MSB for 16-color LUT 3:1 W Foreground color 11 Select one of 8 color from color LUT Add Byte0[4] as MSB for 16-color LUT. 0 W Background color 00 Bit[2] Select one of 8 color from color LUT Byte 1 Bit Mode Function 7:0 W Character Select [7:0] Byte 2 Bit Mode Function 7:6 W Background color 00 Bit[1:0] Select one of 8 color from color LUT Add Byte0[4] as MSB for 16-color LUT. While 0 is special for transparent 5:3 W Foreground color 10 Select one of 8 color from color LUT Add Byte0[4] as MSB for 16-color LUT. 2:0 W Foreground color 01 Select one of 8 color from color LUT Add Byte0[4] as MSB for 16-color LUT.
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Character command (For 4-bit RAM font) Byte 0 Bit Mode Function 7 W 1 6 W Character Blinking effect 0: Disable 1: Enable 5:4 W 01 (Font type 00: 1-bit RAM Font 01: 4-bit RAM Font 1x: 2-bit RAM Font) 3:0 W (for Byte1[7] = 0) select one color from 16-color LUT as background (for Byte1[7] = 1) Red color level MSB 4 bits for 8 bits color level (LSB 4 bits are 1111) Byte 1 Bit Mode Function 7 W 0: 4bit Look Up Table, 0000'b is transparent. 1: 3bit specify R,G,B pattern, color level defined in Byte0[3:0],Byte2. One mask bit defines foreground or background. 6:0 W Character Select [6:0] l 4-bit look-up table mode column space background l 4-bit look-up table mode pixel 0000, byte0[3:0] 0000 transparent. l true color pixel 0000 transparent Byte 2 Bit Mode Function 7:4 W (for Byte1[7] = 1) Green color level MSB 4 bits for 8 bits color level (LSB 4 bits are 1111) 3:0 W (for Byte1[7] = 1) Blue color level MSB 4 bits for 8 bits color level (LSB 4 bits are 1111)
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window 6 window 5 window 4
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T
A
window 3
window 7
window 2 window 1 window 0 Display Priority
We have four windows with gradient and four windows without gradient, the window priority is as above, character should be always on the top layer of the window.
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Pattern gen. Use OSD to replace display pattern generator. Chess Board: make a font as below
If we want to fill to the full 1280x1024 screen with character, we need 1280*1024 pixels. Required character is: Using 12*18 font 1280/12 = 106.7 -> 107 1024/18 = 56.9 -> 57 107*57 = 6099 character
The required number of character map is larger than RAM size. We must turn on double width or double height function to reduce the half of character map. So the basic unit to chessboard is 2x2 pixel. You can use larger chessboard instead of 2x2 pixels unit, such as 4x4 and so on. Gray level 121
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We can display 256 gray level by gradient window, 8 and 16 gray level by character map. 32 and 64 gray level is not supported.
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Electric Specification
DC Characteristics
Table 3 Absolute Maximum Ratings
PARAMETER Voltage on VDD Voltage on Input (5V tolerant) Voltage on Output or I/O or NC Electrostatic Discharge Latch-Up Ambient Operating Temperature Storage temperature (plastic) Thermal Resistance (Junction to Air) SYMBOL VVDD VIN VIO VESD ILA TA TSTG JA MIN -1 -1 -1 TYP
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0 -55
MAX 4.6 5.5 4.6 2.5 100 70 125 18
UNITS V V V kV mA C C C/W
Table 4 DC Characteristics/Operating Condition
(0mA
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2.4 GND 2.0 100 50 -10 -20
VDD 0.5 0.8 300 150 +10 +20
V V V V A A
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AC Characteristics
Input Signal
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ICLK
TIPDS TIPDH
Data Port
ICLK
TIPCS TIPCH
Control Signals
Figure 17 Input Signal Timing
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Symbol TIPCS TIPCH TIPDS TIPDH
Parameter Min Input control signals setup time for ICLK 2 Input control signals hold time for ICLK 1 Input data setup time for ICLK 2 Input data hold time for ICLK 1
Max
Unit ns ns ns ns
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Output Signal
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DCLK
TOPDS TOPDH
Data Port
DCLK
TOPCS TOPCH
Control Signals
Figure 18 Output Signal Timing
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Symbol TOPCS TOPCH TOPDS TOPDH
Parameter Output control signals setup time for Output DCLK control signals hold time for Output DCLK data setup time for DCLK Output data hold time for DCLK
Min 4 1 4 1
Max
Unit ns ns ns ns
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Serial Port Signal
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SCLK
TSPIS TSPIH
SDI
SCLK
TSPOS TSPOH
SDO
Figure 19 Serial Port Signal Timing
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Symbol TSPIS TSPIH TSPOS TSPOH
Parameter Serial port input signal setup time for Serial SCLK port input signal hold time for Serial SCLK port output signal setup time for Serial SCLK port output signal for SCLK
Min 2 8 1/3 1/2
Max
Unit ns ns TCK TCK
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1.44.4 PLL
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Tcycle
3.3V 2.8V
DCLK
1.65V 0.8V
Tor
Tof Max 2.0 2.0 55 250 300 Unit ns ns % ps ps
Electrical Characteristics
Mix Type Characteristics Symbol Conditions Output rise time (20pf Load) Tor From 0.8V to 2.0V,Vdd=3.3V Output fall time (20pf Load) Tof From 2.0V to 0.8V,Vdd=3.3V Duty cycle (20pf Load, at 1.5V) Tduty DCLK 45 50 Clock Skew (20pf Load, at 1.5V) Tskw1 DCLK to DCLK Jitter, Absolute (20pf Load) Tj1 DCLK
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Mechanical Specification 1.45 128 Pin Package
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Note:
Symbol A A1 A2 b c D E e HD HE L L1 y Dimension in inch Min Type Max 0.134 0.004 0.010 0.036 0.102 0.112 0.122 0.005 0.009 0.013 0.002 0.006 0.010 0.541 0.551 0.561 0.778 0.787 0.797 0.010 0.020 0.030 0.665 0.677 0.689 0.902 0.913 0.925 0.027 0.035 0.043 0.053 0.063 0.073 0.004 12 0 Dimension in mm Min Type Max 3.40 0.10 0.25 0.91 2.60 2.85 3.10 0.12 0.22 0.32 0.05 0.15 0.25 13.75 14.00 14.25 19.75 20.00 20.25 0.25 0.5 0.75 16.90 17.20 17.50 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 0.10 0 12
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1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion. 3.Controlling dimension: Millimeter 4.General appearance spec. should be based on final visual inspection spec. TITLE : 128LD QFP ( 14x20 mm*2 ) PACKAGE OUTLINE -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: APPROVE DOC. NO. 530-ASS-P004 VERSION 1 PAGE OF CHECK DWG NO. Q128 - 1 DATE MAR. 25.1997 REALTEK SEMI-CONDUCTOR CO., LTD
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